[Gems-users] How to configure a shared L2 cache beyond single chip?

["Lide Duan" <leaderduan@xxxxxxxxx>]

I found from GEMS wiki that those two-level CMP protocols (e.g. MOESI_CMP_directory, MS_MOSI_CMP_directory, MOESI_CMP_token, etc) assume a shared L2 cache *within one chip*. Does that mean there is no chance for a processor on chip0 to access some L2 cache bank on chip1 (assuming a two-chip CMP)?

If I want to simulate a multi-chip CMP system which has a shared L2 cache among all the chips, i.e. the processors can access L2 banks on other chips, how should I configure Ruby? Does it make sense that all the processors are set within one chip (so that the whole L2 cache is shared in the protocol) but the network file (using FILE_SPECIFIED topology) is specified in a way that some differences exist between "the same chip" and "different chips", e.g. larger latency and lower bandwidth for the links connected between different chips, ?

Any suggestion is appreciated. Thanks,
Lide