What commands do you issue to Simics before you load ruby?
Also, what versions of GEMS and Simics are you using?
wangzuo wrote:
> gems-users，您好！
>
> I have run apache benmark using MESI_SCMP_directory protocol, and get such dump status information:
>
>
> ================ Begin System Configuration Print ================
>
> ......
>
> ================ End System Configuration Print ================
>
> Real time: Jan/17/2008 10:32:01
>
> Profiler Stats
> --------------
> Elapsed_time_in_seconds: 25
> Elapsed_time_in_minutes: 0.416667
> Elapsed_time_in_hours: 0.00694444
> Elapsed_time_in_days: 0.000289352
>
> Virtual_time_in_seconds: 12.25
> Virtual_time_in_minutes: 0.204167
> Virtual_time_in_hours: 0.00340278
> Virtual_time_in_days: 0.00340278
>
> Ruby_current_time: 193530
> Ruby_start_time: 1
> Ruby_cycles: 193529
>
> mbytes_resident: 348.613
> mbytes_total: 348.633
> resident_ratio: 1
>
> Total_misses: 0
> total_misses: 0 [ 0 0 0 0 0 0 0 0 ]
> user_misses: 0 [ 0 0 0 0 0 0 0 0 ]
> supervisor_misses: 0 [ 0 0 0 0 0 0 0 0 ]
>
> instruction_executed: 2598495 [ 242009 13500 441166 738084 20083 9062 396331 738260 ]
> simics_cycles_executed: 6198160 [ 774119 774119 774332 775118 775118 775118 775118 775118 ]
> cycles_per_instruction: 0.595819 [ 0.799677 14.3355 0.438676 0.262205 9.63646 21.3561 0.488301 0.262142 ]
> misses_per_thousand_instructions: 0 [ 0 0 0 0 0 0 0 0 ]
>
> transactions_started: 0 [ 0 0 0 0 0 0 0 0 ]
> transactions_ended: 0 [ 0 0 0 0 0 0 0 0 ]
> instructions_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
> cycles_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
> misses_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ]
>
> L1D_cache cache stats:
> L1D_cache_total_misses: 8566
> L1D_cache_total_demand_misses: 8566
> L1D_cache_total_prefetches: 0
> L1D_cache_total_sw_prefetches: 0
> L1D_cache_total_hw_prefetches: 0
> L1D_cache_misses_per_transaction: 8566
> L1D_cache_misses_per_instruction: 0.00329653
> L1D_cache_instructions_per_misses: 303.349
>
> L1D_cache_request_type_LD: 68.3633%
> L1D_cache_request_type_ST: 6.12888%
> L1D_cache_request_type_ATOMIC: 25.5078%
>
> L1D_cache_access_mode_type_SupervisorMode: 8039 93.8478%
> L1D_cache_access_mode_type_UserMode: 527 6.15223%
> L1D_cache_request_size: [binsize: log2 max: 64 count: 8566 average: 4.45646 | standard deviation: 2.99039 | 0 68 2869 3278 2343 0 0 8 ]
>
> L1I_cache cache stats:
> L1I_cache_total_misses: 2074
> L1I_cache_total_demand_misses: 2074
> L1I_cache_total_prefetches: 0
> L1I_cache_total_sw_prefetches: 0
> L1I_cache_total_hw_prefetches: 0
> L1I_cache_misses_per_transaction: 2074
> L1I_cache_misses_per_instruction: 0.000798156
> L1I_cache_instructions_per_misses: 1252.89
>
> L1I_cache_request_type_IFETCH: 100%
>
> L1I_cache_access_mode_type_SupervisorMode: 1012 48.7946%
> L1I_cache_access_mode_type_UserMode: 1062 51.2054%
> L1I_cache_request_size: [binsize: log2 max: 4 count: 2074 average: 4 | standard deviation: 0 | 0 0 0 2074 ]
>
> L2_cache cache stats:
> L2_cache_total_misses: 0
> L2_cache_total_demand_misses: 0
> L2_cache_total_prefetches: 0
> L2_cache_total_sw_prefetches: 0
> L2_cache_total_hw_prefetches: 0
> L2_cache_misses_per_transaction: 0
> L2_cache_misses_per_instruction: 0
> L2_cache_instructions_per_misses: NaN
>
> L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
>
> The L2 misses information is zero? what is wrong?
>
> I use tester.exec to trace how two simple instructions (load 0x400 by processor 4 and load 0x400 by processor1) excute under :
>
> Testing clear stats...Done.
> Reading trace from file 'little.trace'...
> 1 4 -1 Seq Begin > [0x400, line 0x400] LD
> 4 0 4 L1Cache Load NP>IS [0x400, line 0x400]
> 136 0 0 L2Cache L1_GETS NP>ISS [0x400, line 0x400] [NetDest (3) 0 0 0 0 0 0 0 0 - 0 0 0 0 1 0 0 0 - 0 0 0 0 0 0 0 0 - ]
> 261 0 0 Directory Fetch I>I [0x400, line 0x400]
> 503 0 0 L2Cache Mem_Data ISS>MT_MB [0x400, line 0x400]
> 737 4 -1 Seq Done > [0x400, line 0x400] 736 cycles NULL LD Yes
> 737 0 4 L1Cache Data_Exclusive IS>E [0x400, line 0x400]
> 763 0 0 L2Cache Exclusive_Unblock MT_MB>MT [0x400, line 0x400]
> 801 1 -1 Seq Begin > [0x300, line 0x300] LD
> 803 0 1 L1Cache Load NP>IS [0x300, line 0x300]
> 917 0 0 L2Cache L1_GETS NP>ISS [0x300, line 0x300] [NetDest (3) 0 0 0 0 0 0 0 0 - 0 1 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 - ]
> 1042 0 4 Directory Fetch I>I [0x300, line 0x300]
> 1381 0 0 L2Cache Mem_Data ISS>MT_MB [0x300, line 0x300]
> 1496 1 -1 Seq Done > [0x322, line 0x300] 695 cycles NULL LD Yes
> 1496 0 1 L1Cache Data_Exclusive IS>E [0x300, line 0x300]
> 1504 0 0 L2Cache Exclusive_Unblock MT_MB>MT [0x300, line 0x300]
>
> I find somethings are not normal.L2 seems do not carry L1_GETS action but send it to others "[NetDest (3) 0 0 0 0 0 0 0 0 - 0 0 0 0 1 0 0 0 - 0 0 0 0 0 0 0 0 - ]". Can anyone tell me why? The following is what I get from the MOESI_CMP_directoy protocal by excuting the same two instructions.
>
> 136 0 0 L2Cache L1_GETS NP>IGS [0x400, line 0x400]
> 261 0 0 Directory GETS I>IS [0x400, line 0x400]
>
>
> 致
> 礼！
>
>
> wangzuo
> qiushui@xxxxxxxxxx
> 2008-01-17
>
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