Re: [Gems-users] cache protocol problem

[Dan Gibson <degibson@xxxxxxxx>]

(1)MESI_SCMP_L2bankDirectory co-locates directory state with the L2s,
and the directories (like the L2 banks) are interleaved by address.
Instructions and data are still stored in the L2, but the tags at the L2
are also sufficient to name all potential sharers of the block, hence
also serving as a directory.

(2) 0 L2 misses is not normal, though it could be a difference in how
the protocol profiles itself. Look at various miss statistics and see if
any make sense -- Total_misses, for instance.

(3) MOESI_CMP_directory is a two-level hierarchical directory-directory
protocol, which I believe is usable for both inter- and intra-chip
coherence. The Cadillac of coherence, if you will. I don't know what
MOESI_CMP_homedirectory is.

Regards,
Dan

wangzuo wrote:
> gems-users，您好！
>
> 	    I have three questions which list below:
> 		
> 		(1)it is hard to understand this sentence in gems's doc "MESI_SCMP_L2bankDirectory 
> Description: A Single-CMP protocol using L2 caches as directories. Home L2 bank is interleaved by block address. L2 is nominally shared amongst all processors." what "using L2 caches as directories" means? what "Home L2 bank"means? I have got 0 L2 cache misses in simulation, it is because of the "MESI_SCMP is only for single-chip so use L2 to store directories but not for data or instruction"? I am so confused about this. The following is what I use tester to see what happens:
>
> Testing clear stats...Done.
> Reading trace from file 'little.trace'...
>       1   4  -1        Seq               Begin       >       [0x400, line 0x400] LD
>       4   4   0    L1Cache                Load     NP>IS     [0x400, line 0x400] 
>      14   4   0    L2Cache             L1_GETS     NP>ISS    [0x400, line 0x400] [NetDest (3) 0 0 0 0 0 0 0 0  - 0 0 0 0 1 0 0 0  - 0 0 0 0 0 0 0 0  - ]
>      26   0   0  Directory               Fetch      I>I      [0x400, line 0x400] 
>      39   4   0    L2Cache            Mem_Data    ISS>MT_MB  [0x400, line 0x400] 
>     149   4  -1        Seq                Done       >       [0x400, line 0x400] 148 cycles Directory LD Yes
>     149   4   0    L1Cache      Data_Exclusive     IS>E      [0x400, line 0x400] 
>     157   4   0    L2Cache   Exclusive_Unblock  MT_MB>MT     [0x400, line 0x400] 
>     201   1  -1        Seq               Begin       >       [0x300, line 0x300] LD
>     204   1   0    L1Cache                Load     NP>IS     [0x300, line 0x300] 
>     211   1   0    L2Cache             L1_GETS     NP>ISS    [0x300, line 0x300] [NetDest (3) 0 0 0 0 0 0 0 0  - 0 1 0 0 0 0 0 0  - 0 0 0 0 0 0 0 0  - ]
>     440   4   0  Directory               Fetch      I>I      [0x300, line 0x300] 
>     455   1   0    L2Cache            Mem_Data    ISS>MT_MB  [0x300, line 0x300] 
>     459   1  -1        Seq                Done       >       [0x322, line 0x300] 258 cycles Directory LD Yes
>     459   1   0    L1Cache      Data_Exclusive     IS>E      [0x300, line 0x300] 
>     470   1   0    L2Cache   Exclusive_Unblock  MT_MB>MT     [0x300, line 0x300]
>
> 		(2)the same 0 L2 cache misses in simulation comes with MESI_CMP_directory. Is it normal?
>
> 		(3) what is the difference between MOESI_CMP_directory and MOESI_CMP_homedirectory?
>   
>
> 　　　　　　　　致
> 礼！
>  				
>
> 　　　　　　　　wangzuo
> 　　　　　　　　qiushui@xxxxxxxxxx
> 　　　　　　　　　　2008-01-16
>
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