The only request is from P3. The request reaches the global directory/memory controller at time 339. But then it appears the same request is continually recycled. It appears either a second identical request message somehow got injected into the interconnect or that the directory/memory controller failed to remove the request. P3 ends up getting permission, but then the directory gets another request from P3 which is forwarded to itself. The protocol doesn't expect this behavior.
Did you modify the protocol?
--Mike
On Jan 9, 2008 4:46 PM, avinankumar vellore < avinankumar@xxxxxxxxx> wrote:
Dear Mike,
Thanks for your reply. Following is the trace
1002 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1005 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1008 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1011 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1014 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1017 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1020 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1023 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1026 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1029 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1032 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1035 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1038 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1041 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1044 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1047 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1050 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1053 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1056 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1059 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1062 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1065 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1068 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1071 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1074 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1077 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1080 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1083 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1086 0 1 Directory GETS IS>IS [0x1d2c1e40, line 0x1d2c1e40]
1089 0 1 Directory Exclusive_Unblock IS>M [0x1d2c1e40, line 0x1d2c1e40]
1089 0 1 Directory GETS M>MO [0x1d2c1e40, line 0x1d2c1e40]
1333 0 0 L2Cache Fwd_GETS ILX>IFGS [0x1d2c1e40, line 0x1d2c1e40]
1503 0 3 L1Cache Fwd_GETS M>O [0x1d2c1e40, line 0x1d2c1e40]
1669 0 0 L2Cache Data IFGS>ILO [0x1d2c1e40, line 0x1d2c1e40]
Warning: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2089: m_id is 0
Warning: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2090: m_version is 0
Warning: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2091: g_eventQueue_ptr->getTime() is 1839
Warning: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2092: addr is [0x1d2c1e40, line 0x1d2c1e40]
Warning: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2093: event is Data
Warning: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2094: state is ILO
Fatal Error: in fn TransitionResult L2Cache_Controller::doTransitionWorker(L2Cache_Event, L2Cache_State, L2Cache_State&, const Address&) in generated/MOESI_CMP_directory/L2Cache_Transitions.C:2095: Invalid transition
I also have a wierd situation. Even before I start running the benchmark in the target machine, I am getting this error. Following is the sequence of instructions which I used for starting the simulation
simics> read-configuration
after-4p-benchmark-load.conf
simics> instruction-fetch-mode instruction-fetch-trace
[cpu0 info] Note that on this cpu, instruction-fetch-trace is implemented using instruction-cache-access-trace with a suitable cache line size.
[cpu1 info] Note that on this cpu, instruction-fetch-trace is implemented using instruction-cache-access-trace with a suitable cache line size.
[cpu2 info] Note that on this cpu, instruction-fetch-trace is implemented using instruction-cache-access-trace with a suitable cache line size.
[cpu3 info] Note that on this cpu, instruction-fetch-trace is implemented using instruction-cache-access-trace with a suitable cache line size.
simics> istc-disable
Turning I-STC off and flushing old data
simics> dstc-disable
Turning D-STC off and flushing old data
simics> cpu-switch-time 1
The switch time will change to 1 cycles (for CPU-0) once all processors have synchronized.
simics> magic-break-enable
simics> break-hap "Core_Magic_Instruction"
simics> load-module ruby
successful installation of the ruby timing model.
simics> ruby0.setparam g
_Argument error: argument number 2 is missing in '<ruby>.setparam';
integer expected.
SYNOPSIS: <ruby>.setparam "name" value
simics> ruby0.setparam g_NUM_L2_BANKS 1
simics> ruby0.setparam g_NUM_PROCESSORS 4
simics> ruby0.setparam g_PROCS_PER_CHIP 4
simics> ruby0.init
Ruby Timing Mode
Warning: optimizations not enabled.
Creating event queue...
Creating event queue done
Creating system...
Processors: 4
Creating system done
Ruby initialization complete
simics> ruby0.debug-start-time 1000
simics> ruby0.debug-output-file error2.log
simics> c
Moments after I type the command 'c', I am getting this error. I would really appreciate if you could help me in resolving this issue.
Thank you for your time.
Regards,
AvinanOn Jan 9, 2008 11:42 AM, Mike Marty <
mike.marty@xxxxxxxxx> wrote:
Try to get a trace for the invalid transitions. Start the trace about 10,000 or so cycles in advance of the invalid transition and then filter by the block address that it happens for. Send this to the list and I'll see what I can do.
The following Simics command starts a trace at time 1324352
ruby0.debug-start-time '1324352'
Then just grep on the block address
--Mike
_______________________________________________
Gems-users mailing list
Gems-users@xxxxxxxxxxx
https://lists.cs.wisc.edu/mailman/listinfo/gems-users
Use Google to search the GEMS Users mailing list by adding "site:https://lists.cs.wisc.edu/archive/gems-users/
" to your search.
_______________________________________________
Gems-users mailing list
Gems-users@xxxxxxxxxxx
https://lists.cs.wisc.edu/mailman/listinfo/gems-users
Use Google to search the GEMS Users mailing list by adding "site:https://lists.cs.wisc.edu/archive/gems-users/
" to your search.
|
![[Computer Systems Lab]](http://www.cs.wisc.edu/pics/csl_logo.gif){kind=logo}