[Gems-users] No misses in the L1 Icache?

["张量" <congwu.zhang@xxxxxxxxx>]

hi,everyone!
I'm using gems-2.0 and the MESI_SCMP_bankdirectory protocol. I want to check the behavior of shared L2 cache when multiple 
threads are co-scheduled. I also want to consider the impact of misses in the L1 ICache.
I use ruby0.dump-stats command to get the statistics of all the caches ,but I find that there is no miss in the L1 Icache at all.
Why?
Here are the results:                           


L1D_cache cache stats:
  L1D_cache_total_misses: 5850028
  L1D_cache_total_demand_misses: 5850028
  L1D_cache_total_prefetches: 0
  L1D_cache_total_sw_prefetches: 0
  L1D_cache_total_hw_prefetches: 0
  L1D_cache_misses_per_transaction: 
5.85003e+06
  L1D_cache_misses_per_instruction: 0.00193862
  L1D_cache_instructions_per_misses: 515.832

  L1D_cache_request_type_LD:   85.2473%
  L1D_cache_request_type_ST:   12.734%
  L1D_cache_request_type_ATOMIC:   
2.01879%

  L1D_cache_access_mode_type_SupervisorMode:   3844927    65.7249%
  L1D_cache_access_mode_type_UserMode:   2005101    34.2751%
  L1D_cache_request_size: [binsize: log2 max: 64 count: 5850028 average: 
5.44848 | standard deviation: 5.48723 | 0 1222116 818582 861025 2912878 0 0 35427 ]

L1I_cache cache stats:
  L1I_cache_total_misses: 0
  L1I_cache_total_demand_misses: 0
  L1I_cache_total_prefetches: 0
  L1I_cache_total_sw_prefetches: 0
  L1I_cache_total_hw_prefetches: 0
  L1I_cache_misses_per_transaction: 0
  L1I_cache_misses_per_instruction: 0
  L1I_cache_instructions_per_misses: NaN

  L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]

L2_cache cache stats:
  L2_cache_total_misses: 0
  L2_cache_total_demand_misses: 0
  L2_cache_total_prefetches: 0
  L2_cache_total_sw_prefetches: 0
  L2_cache_total_hw_prefetches: 0
  L2_cache_misses_per_transaction: 0
  L2_cache_misses_per_instruction: 0
  L2_cache_instructions_per_misses: NaN

  L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]