Hi,
I have a question regarding the latency between the sequencer and the
controller that is defined as SEQUENCER_TO_CONTROLLER_LATENCY. Does this
model a component that is normally found in real hardware? I don't see
this latency as natural as the latencies related to the L1 & L2 cache,
directory etc. If this is only a simulation artifact, is it possible to
set it to zero without causing any problems?
Same question applies to the RECYCLE_LATENCY - is it a latency that
models something that can be seen in real hardware or is it a simulation
artifact?
Thanks.
Regards,
Mladen
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