That latency assumes a perfect directory cache, or a directory implemented in SRAM
--Mike
On Thu, Apr 3, 2008 at 6:05 PM, Niket < niketa@xxxxxxxxxxxxx> wrote:
Hi all,
I had a question regarding the latency that the directory protocols
assume for looking up on-chip sharers. For instance, while sending out
invalidates to all L1 shares on a GETX event, the latency assumed is
L2_REQUEST_LATENCY which is of the order of 4 cycles. Since this
invalidation request requires a sharer list lookup, shouldn't this
latency be more ? Something like DIRECTORY_LATENCY which is of the order
of 80 cycles ?
action(tt_issueSharedInvalidateIntL1copiesRequest, "\t",
desc="invalidate all L1 S copies") {
enqueue(L1RequestIntraChipL2Network_out, RequestMsg,
latency="L2_REQUEST_LATENCY") {
out_msg.Address := address;
out_msg.Type := CoherenceRequestType:INV_S;
out_msg.RequestorMachId := machineID;
out_msg.Destination := L2cacheMemory[address].Sharers;
out_msg.MessageSize := MessageSizeType:Control;
}
}
Cheers,
Niket
_______________________________________________
Gems-users mailing list
Gems-users@xxxxxxxxxxx
https://lists.cs.wisc.edu/mailman/listinfo/gems-users
Use Google to search the GEMS Users mailing list by adding "site:https://lists.cs.wisc.edu/archive/gems-users/" to your search.
|