Re: [Gems-users] Excessive Cache Misses

[Mike Marty <mikem@xxxxxxxxxxx>]

>
> We were using 2 processors.
>
> Unfortunately (or fortunately) you were right.  When I run the MI_example os idling, I get hundreds of thousands of cache misses, while the MOS_SMP_bcast only gives me around 200.  This seems much more reasonable.
>
> I guess there must be some fundamental problems with the MI_example.
>

Well one problem with MI_example is that it doesn't allow shared copies of
instructions.  This can be problematic...especially when there is any OS
activity (e.g.  taking any exception)


> One more question, since we will start using the MOSI protocol, what does the line:
> MessageBuffer mandatoryQueue, ordered="false" mean?
>

This is in all protocols and is the Processor/Cache interface.  The Ruby
Sequencer will initiate a request to the cache controller by placing a
request on this MessageBuffer.  The "ordered" property specifies whether
the MessageBuffer enforces FIFO ordering...it is probably irrelevant for
this buffer.

--Mike