Re: [Gems-users] tracking cache stats

[Dan Gibson <degibson@xxxxxxxx>]

I'm not entirely sure this piece of code is going to do what you want:

if(request.getType() == CacheRequestType_IFETCH && !hit) {
   m_il1_misses[cpuid]++;
   m_ul2_accesses[cpuid]++;
 }
 else if(request.getType() == !CacheRequestType_IFETCH && !hit) {
   m_dl1_misses[cpuid]++;
   m_ul2_accesses[cpuid]++;
 }

Notably, if memory serves, CacheRequestType is an enum, so applying 
logical not to CacheRequestType_IFETCH does not evaluate to the other 
cache request types. I would think that the second if condition will 
always evaluate to false.
As for profiling the L2, you can just modify the proflier's 
addPrimaryStatSample() to also track L2 misses on a per-processor basis. 
(Profiler.[Ch])
Regards,
Dan

Mladen Nikitovic wrote:

> Hi,
>
> I posted a message a while ago regarding tracking L1 cache stats when 
> using the MSI_MOSI_CMP_directory protocol. I wanted to see the accesses 
> and misses divided between the processors, so got the tip that I should 
> add my code to the makeRequest function within the Sequencer. This is my 
> added code (did I understand your tip correctly?), however I don't see 
> how I can track the L2 misses. Can you give me a pointer where to look?
> Regards,
> Mladen
>
> // Called by Driver (Simics or Tester).
> void Sequencer::makeRequest(const CacheMsg& request) {
>  int cpuid;
>
>  assert(isReady(request));
>  bool write = (request.getType() == CacheRequestType_ST) ||
>    (request.getType() == CacheRequestType_ST_XACT) ||
>    (request.getType() == CacheRequestType_LDX_XACT) ||
>    (request.getType() == CacheRequestType_ATOMIC);
>
>  cpuid = m_chip_ptr->getID()*RubyConfig::numberOfProcsPerChip()+m_version;
>
>  if(request.getType() == CacheRequestType_IFETCH)
>    m_il1_accesses[cpuid]++;
>  else
>    m_dl1_accesses[cpuid]++;
>
>  if (TSO && (request.getPrefetch() == PrefetchBit_No) && write) {
>    assert(m_chip_ptr->m_L1Cache_storeBuffer_vec[m_version]->isReady());
>    m_chip_ptr->m_L1Cache_storeBuffer_vec[m_version]->insertStore(request);
>    return;
>  }
>
>  bool hit = doRequest(request);
>
>  if(request.getType() == CacheRequestType_IFETCH && !hit) {
>    m_il1_misses[cpuid]++;
>    m_ul2_accesses[cpuid]++;
>  }
>  else if(request.getType() == !CacheRequestType_IFETCH && !hit) {
>    m_dl1_misses[cpuid]++;
>    m_ul2_accesses[cpuid]++;
>  }
> }
>
>
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