[Gems-users] tracking cache stats

[Mladen Nikitovic <mladen@xxxxxx>]

Hi,

I posted a message a while ago regarding tracking L1 cache stats when 
using the MSI_MOSI_CMP_directory protocol. I wanted to see the accesses 
and misses divided between the processors, so got the tip that I should 
add my code to the makeRequest function within the Sequencer. This is my 
added code (did I understand your tip correctly?), however I don't see 
how I can track the L2 misses. Can you give me a pointer where to look?
Regards,
Mladen

// Called by Driver (Simics or Tester).
void Sequencer::makeRequest(const CacheMsg& request) {
 int cpuid;

 assert(isReady(request));
 bool write = (request.getType() == CacheRequestType_ST) ||
   (request.getType() == CacheRequestType_ST_XACT) ||
   (request.getType() == CacheRequestType_LDX_XACT) ||
   (request.getType() == CacheRequestType_ATOMIC);

 cpuid = m_chip_ptr->getID()*RubyConfig::numberOfProcsPerChip()+m_version;

 if(request.getType() == CacheRequestType_IFETCH)
   m_il1_accesses[cpuid]++;
 else
   m_dl1_accesses[cpuid]++;

 if (TSO && (request.getPrefetch() == PrefetchBit_No) && write) {
   assert(m_chip_ptr->m_L1Cache_storeBuffer_vec[m_version]->isReady());
   m_chip_ptr->m_L1Cache_storeBuffer_vec[m_version]->insertStore(request);
   return;
 }

 bool hit = doRequest(request);

 if(request.getType() == CacheRequestType_IFETCH && !hit) {
   m_il1_misses[cpuid]++;
   m_ul2_accesses[cpuid]++;
 }
 else if(request.getType() == !CacheRequestType_IFETCH && !hit) {
   m_dl1_misses[cpuid]++;
   m_ul2_accesses[cpuid]++;
 }
}