Re: [Gems-users] Invalidate directory entry

[Mike Marty <mikem@xxxxxxxxxxx>]

The L2 controller handles intra-CMP coherence.  Then there is a global
directory implemented in MSI_MOSI_CMP_directory-dir.sm to track coherence
between CMP chips.  This directory is assumed to be stored in DRAM.

> Mike, Thanks for your prompt reply. So there is actually no directory stored
> on each chip to keep the state of a memory address?
>
> Lei
> ----- Original Message -----
> From: "Mike Marty" <mikem@xxxxxxxxxxx>
> To: "Lei Yang" <lya755@xxxxxxxxxxxxxxxxxxxx>; "Gems Users"
> <gems-users@xxxxxxxxxxx>
> Sent: Wednesday, January 10, 2007 4:59 PM
> Subject: Re: [Gems-users] Invalidate directory entry
>
>
> > This protocol stores the directory state in the L2 cache tag.  The
> > L2_Replacement will eventually cause the L2 controller to deallocate the
> > L2 cache tag.  When both the TBE (for handling the replacement of shared
> > or dirty data) and the L2 tag is deallocated, then the Directory state is
> > gone and considered NP (Not Present), equivalent to I.
> >
> > For example, replacing M will deallocate L2 tag immediately but allocate a
> > TBE (to handle the demand miss causing the replacement in parallel).
> > Eventually this transition occurs, which will actually result in state NP
> > (Not Present) even though the target transition state is L2_I.  If there
> > is nothing to hold the state L2_I, then the state is L2_NP
> >
> >  transition(L2_MIN, Dir_WB_ack, L2_I) {
> >    s_deallocateTBE;
> >    l_popForwardedRequestQueue;
> >  }
> >
> >
> > That was a confusing explanation.
> >
> > --Mike
> >
> >
> > > Hi list, >
> >> I'm looking at MSI_MOSI_CMP_directory-L2cache.sm file and I'm wondering
> >> after a L2_Replacement, where/how did the protocol change the state of
> >> the corresponding directory entry to invalidate that? Please advise.
> >>
> >> Thanks,
> >> Lei
> >
> >
>
>