Re: [Gems-users] Same L1D cache miss and L2 cache miss in MESI_CMP_filter_directory

["Dave Z." <zhu_dave@xxxxxxxxx>]

Hi,

I don't know the specific details of the protocol you're working on, but if the *-L1cache.sm uses profile_miss rather than profile_L1Cache_miss and you set REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH to true, then you might get the same number of misses for both L1D and L2. At least, that was the case for me...

Hope it helps,

Dave

----- Original Message ----
From: Arnab Sinha <sinha@xxxxxxxxxxxxx>
To: gems-users@xxxxxxxxxxx
Sent: Friday, December 7, 2007 8:29:31 AM
Subject: [Gems-users] Same L1D cache miss and L2 cache miss in MESI_CMP_filter_directory

Hi,

 

I am simulating some SPLASH benchmarks (in LogTM framework) in GEMS 2.0 with the coherence protocol ʽMESI_CMP_filter_directoryʼ. In most of the benchmarks, I am getting same number of L1 data cache misses and L2 misses. Is it because that I set REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: true?

 

Can anybody suggest?

 

Thanks,

Arnab

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