Re: [Gems-users] Tracking L1D and L2 misses in Ruby

["Mike Marty" <mike.marty@xxxxxxxxx>]

Tushar,

In the generated L1Cache_Controller.C file, you will see all the actions that are called when handling a state transition.  In the case of an L1 miss, there is an action that creates a message and enqueues it into a MessageBuffer.  The Ruby interconnect model will deliver the message to a MessageBuffer of the corresponding L2 controller.  Likewise, on an L2 miss, there is an action to deliver a message to the Memory/Directory controller.

Our strategy for prefetching in the past has been to create a Prefetching object that is tied to a special MessageBuffer in the L2 controller.  The object will inject prefetch messages handled by the L2 controller to carry out the rest of the actions required.

--Mike

On Dec 5, 2007 12:22 AM, Tushar Krishna (tkrishna@xxxxxxxxxxxxx) <tkrishna@xxxxxxxxxxxxx > wrote:

Hi,
I am trying to track how a memory request moves through ruby once it has been called by Simics. I am using the MSI_MOSI_CMP_directory protocol. I have declared 16 cores on one chip hence I have 16 L1 caches and ONE shared L2.

I have been able to see how a L1D miss request moves from Sequencer.C to L1Cache_Wakeup.C to L1Cache_Transitions.C to L1Cache_Controller.C. Could anyone tell me which function(s) in the code send the request to L2 that causes L2Cache_Wakeup.C to come into effect? (L1Cache_Transitions.C shows the possible state changes of L1 cache lines and I guess that an I to S or an I to M for instance would result in L2 being accessed).
And once L2 wakes up and L2Cache_Transition.C comes into effect, where in the code is the request to main Memory being simulated in case of a L2 miss?
I aim to add a Prefetch unit at L2 which would get extra lines from memory on each miss and store them in L2.

Thanks
Tushar

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