[Gems-users] Tracking L1D and L2 misses in Ruby

["Tushar Krishna (tkrishna@xxxxxxxxxxxxx)" <tkrishna@xxxxxxxxxxxxx>]

Hi,
I am trying to track how a memory request moves through ruby once it has been called by Simics. I am using the MSI_MOSI_CMP_directory protocol. I have declared 16 cores on one chip hence I have 16 L1 caches and ONE shared L2.

I have been able to see how a L1D miss request moves from Sequencer.C to L1Cache_Wakeup.C to L1Cache_Transitions.C to L1Cache_Controller.C. Could anyone tell me which function(s) in the code send the request to L2 that causes L2Cache_Wakeup.C to come into effect? (L1Cache_Transitions.C shows the possible state changes of L1 cache lines and I guess that an I to S or an I to M for instance would result in L2 being accessed).
And once L2 wakes up and L2Cache_Transition.C comes into effect, where in the code is the request to main Memory being simulated in case of a L2 miss?
I aim to add a Prefetch unit at L2 which would get extra lines from memory on each miss and store them in L2.

Thanks
Tushar