Brianna Sue Bethel wrote:
I think I figured out how to print out the full address in Sequencer.C makeRequest before the isReady function is called.
Now I have a few more clarifying questions:
1) Does one sequencer send requests from all processors? Without Opal, is there more than one sequencer?
Nope. One Sequencer per processor. With and without Opal.
2) When the sequencer calls makeRequest, does this request go into the mandatoryQueue in the .sm file? In other words, is there a way to confirm that a request seen in the sequencer is the same as the request seen in the .sm file MandatoryQueue?
Yes, eventually the Sequencer enqueues the CacheMsg into the
mandatoryQueue of the L1Cache controller (specified with a .sm file).
However the Sequencer also does a tryCacheAccess() to only enqueue
messages that miss in the cache ("fast path" miss...well discussed on
this list).
--Mike
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