Re: [Gems-users] Printing Out Complete Address (with Data Block Bits)

[Mike Marty <mikem@xxxxxxxxxxx>]

Hi Briana,

I'm pretty sure the block bits are masked off in ruby/system/Sequencer.C 
before the request issues to the L1Cache controller.  See the 
issueRequest() function in Sequencer.C.  I suggest that you might add 
another field to CacheMsg to record the original address before masked.  
The CacheMsg is initially filled out in ruby/simics/SimicsProcessor.C in 
the makeRequest() function. 

Hope that helps.

--Mike

Brianna Sue Bethel wrote:
> First of all, thanks for all your help so far.  We are making progress, slowly but surely.
>
> In order for our speculation, we need to be able to compare the full 64 bit address, including the DataBlockBits so we can determine which location in the cache line is being referenced.  Originally in our protocol .sm file we tried to store the 'address' variable which was used in the trigger function.  However, even then, we seem to get the memory address with the data block bits masked off...the last 6 bits are always zero.  
>
> My question is how can we access the ORIGINAL address, without the data block bits being masked to zero?
>
> Thanks, 
> Brianna
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