Re: [Gems-users] Reg. L1 transition counts

[srinivas vadlamani <srinietc@xxxxxxxxx>]

Thanks Mike,

We looked at the generated files and the slicc files
and it seems like the file "StateMachine.C" is the one
that should be changed to distinguish between various
types of L1 transition counts.

We just wanted to verify if there aren't other places
in the system that may have to be modified as well.

Thanks,
Srinivas.
>> We're using MOESI_SMP_hammer cache coherence
protocol
>> to simulate a 2-way Opteron SMP system (1 processor
>> per chip) with private L1 and L2 caches. The
>> transition counts being generated by Ruby for the
L1
>> cache under "Chip Stats" do not seem to distinguish
>> between the individual processor counts or between
the
>> user-mode and supervisor-mode counts.
>>
>> Is it possible to get the L1 transition counts for
>> each processor in the user and supervisor modes?
>>

>You will need to modify the profiling code to
seperate >the transition
>counts to individual processors, and by user and
>supervisor.  See where
>the profileTransition() call is made in the generated
>code.  You will 
>need
>to modify Slicc where the generated file is created.

>--Mike

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