[Gems-users] Reg. L1 transition counts

[srinivas vadlamani <srinietc@xxxxxxxxx>]

Hi,

We're using MOESI_SMP_hammer cache coherence protocol
to simulate a 2-way Opteron SMP system (1 processor
per chip) with private L1 and L2 caches. The
transition counts being generated by Ruby for the L1
cache under "Chip Stats" do not seem to distinguish
between the individual processor counts or between the
user-mode and supervisor-mode counts.

Is it possible to get the L1 transition counts for
each processor in the user and supervisor modes?

Thanks,
Srinivas.

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