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I'm not 100% sure where the L2 cache gets initialized (I've mostly
worked with modifying the L1 cache), however from my experience, I'd
think your best bet is to change the methods in RubyConfig so that
all of the ones querying the L2 cache specify the chip number. Then
you have that function return the appropriate values accordingly.
If you are only using the MSI_MOSI_CMP protocol, it would probably be
easier to just change the generated files so that when querying the
L2 cache size they specify the processors id. Changing the slicc
interface to support that shouldn't be to difficult either, but it
may be easier not to have to start changing that source.
Phil
On Sep 12, 2006, at 1:11 PM, Mario Donato Marino wrote:
Hi!
Suppose we have several L2s, I would like to modify just 1 of the
L2 cache sizes in MSI_MOSI_CMP_directory. ( I could also say I would
like to modify block size, associativity or other parameters).
Should I
modify the protocol specification (via the SLICC utility) or should I
modify the generated codes? What is the most appropriated?
Your help will be greatly appreciated!
Thanks,
Mario
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