Re: [Gems-users] L1 cache miss absent again

[mehmetderin.harmanci@xxxxxxx]

  OK, thanks Mike.

     Derin Harmanci.


Quoting Mike Marty <mikem@xxxxxxxxxxx>:

>
> Setting REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH to "true" relies on the SLICC
> protocol to handle _all_ profiling.  MSI_MOSI_CMP_directory's SLICC
> specification does not profile L1 misses.  You might either want to add
> this code yourself, or set REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH to "false"
> (which is fine for the CMP protocols too, if you are ok with 1-cycle L1
> cache hits).
>
> --Mike
>
>
> >
> >    I'm running a simulation with MSI_MOSI_CMP_directory protocol, for a
> >   configuration of 4 processors. Since I'm using a CMP protocol I've set
> >   the REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH  parameter to true and I do
> >   not have any L1 cache misses, all the misses appear in L2 cache.
> >   I know I asked a similar question before but there I was using the
> >   MOSI_SMP_bcast and setting the above parameter to true. I do not see
> >   why I do not get any L1 cache misses here. Below I give my list of
> >   parameters and the content of my network file.  Any help will be very
> >   much appretiated.
> >
> >     Thanks,
> >
> >        Derin Harmanci
> >
> >
> >
> > ruby0.setparam      g_RANDOM_SEED                1
> >
> >
> >
> >
> > ruby0.setparam      g_trace_warmup_length 10000000
> >
> >
> > ruby0.setparam      SIMICS_RUBY_MULTIPLIER       1
> > ruby0.setparam      OPAL_RUBY_MULTIPLIER         1
> >
> > ruby0.setparam_str  REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH true
> >
> >
> >
> > ruby0.setparam      L1_CACHE_ASSOC               2
> > ruby0.setparam      L1_CACHE_NUM_SETS_BITS       7
> > ruby0.setparam      L2_CACHE_ASSOC               4
> > ruby0.setparam      L2_CACHE_NUM_SETS_BITS      13
> >
> >
> >
> > ruby0.setparam      g_MEMORY_SIZE_BYTES 4294967296
> > ruby0.setparam      g_DATA_BLOCK_BYTES         128
> > ruby0.setparam      g_PAGE_SIZE_BYTES         4096
> > ruby0.setparam      g_NUM_PROCESSORS             4
> > ruby0.setparam      g_NUM_L2_BANKS               4
> > ruby0.setparam      g_NUM_MEMORIES               1
> > ruby0.setparam      g_PROCS_PER_CHIP             4
> >
> >
> >
> >
> >
> > ruby0.setparam      NULL_LATENCY                 0
> > ruby0.setparam      NETWORK_LINK_LATENCY         4
> > ruby0.setparam      CACHE_RESPONSE_LATENCY      12
> > ruby0.setparam      MEMORY_RESPONSE_LATENCY_MINUS_2    268
> > ruby0.setparam      DIRECTORY_LATENCY            2
> > ruby0.setparam      DIRECTORY_CACHE_LATENCY      1
> >
> > ruby0.setparam      ON_CHIP_LINK_LATENCY         1
> > ruby0.setparam      RECYCLE_LATENCY             10
> > ruby0.setparam      TIMER_LATENCY            10000
> >
> > ruby0.setparam_str  PERIODIC_TIMER_WAKEUPS    true
> >
> > ruby0.setparam      L1_REQUEST_LATENCY           3
> > ruby0.setparam      L2_REQUEST_LATENCY           5
> > ruby0.setparam      L2_RECYCLE_LATENCY           5
> >
> > ruby0.setparam      SEQUENCER_TO_CONTROLLER_LATENCY 2
> >
> > ruby0.setparam_str  SINGLE_ACCESS_L2_BANKS   false
> >
> >
> > ruby0.setparam      g_SEQUENCER_OUTSTANDING_REQUESTS 8
> >
> > ruby0.setparam      NUMBER_OF_TBES              16
> > ruby0.setparam      NUMBER_OF_L1_TBES           16
> > ruby0.setparam      NUMBER_OF_L1_TBES           16
> >
> >
> >
> > ruby0.setparam_str  FINITE_BUFFERING         false
> > ruby0.setparam      FINITE_BUFFER_SIZE           0
> > ruby0.setparam      PROTOCOL_BUFFER_SIZE         2
> >
> >
> >
> > ruby0.setparam_str  g_NETWORK_TOPOLOGY     FILE_SPECIFIED
> > ruby0.setparam_str  g_CACHE_DESIGN            SHARED_L2
> >
> >
> > ruby0.setparam      NUMBER_OF_VIRTUAL_NETWORKS   8
> > ruby0.setparam      FAN_OUT_DEGREE               4
> > ruby0.setparam_str  g_PRINT_TOPOLOGY          true
> >
> >
> > ruby0.setparam      g_NUM_DNUCA_BANK_SETS        8
> > ruby0.setparam      g_NUM_DNUCA_BANK_SET_BITS    0
> >
> >
> >
> >
> >
> > ------------------------ NETWORK FILE -----------------------
> >
> >
> > processors:4
> > procs_per_chip:1
> > L2banks:4
> > memories:1
> > bw_unit:10000
> >
> >
> > ext_node:L1Cache:0 int_node:0 link_latency:1 bw_multiplier:64
> > ext_node:L1Cache:1 int_node:1 link_latency:1 bw_multiplier:64
> > ext_node:L1Cache:2 int_node:2 link_latency:1 bw_multiplier:64
> > ext_node:L1Cache:3 int_node:3 link_latency:1 bw_multiplier:64
> > ext_node:Directory:0 int_node:4 link_latency:17 bw_multiplier:64
> >
> > int_node:0 int_node:4 link_latency:1 bw_multiplier:64
> > int_node:1 int_node:4 link_latency:1 bw_multiplier:64
> > int_node:2 int_node:4 link_latency:1 bw_multiplier:64
> > int_node:3 int_node:4 link_latency:1 bw_multiplier:64
> >
> > _______________________________________________
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