Re: [Gems-users] 回复： Re: L1 I cache statistic problem

[Dan Gibson <degibson@xxxxxxxx>]

My guess is that one of two thing will happen:
1) Nothing -- Simics will ignore the stall condition, since the memory_transaction_t is essentially a one-way communication struct (one or two exceptions, but the stallable flag is not one of them).
2) Simics will malfunction in some unexpected way.

I would be very surprised indeed if manually setting the stallable bit would result in correct functionality--but you're welcome to try and report what you find to the list!

Regards,
Dan

guo fei wrote:

what will happen if I manually set a non-stallable instrucion stallable?


Mike Marty <mikem@xxxxxxxxxxx> 写道：

Unfortunately, for x86 targets, Virtutech Simics currently does not allow instructions to be stalled.

 

--Mike

 

----- Original Message -----

From: guo fei

To: gems-users@xxxxxxxxxxx

Sent: Monday, September 11, 2006 10:04 PM

Subject: [Gems-users] L1 I cache statistic problem

hi,

I need some help with regards to Ruby statistic.
I am trying to run Ruby(only,no opal) by using MSI_MOSI_CMP_directory protocol upon a X86 disk image . The statisitc of L1 D cache and L2 cache looks fine. But the L1 I cache statistic are all 0.

I check the source code and find the reason is that for all the memory_transactions ("mem_trans")come from simics, if the transaction type is "mem_trans->s.type ==Sim_Trans_Instr_Fetch", the "mem_trans->s.may_stall" is always 0.  Therefore in the
" SimicsDriver::isUnhandledTransaction(memory_transaction_t* mem_trans)"
function, all the instruction fetch transactions are filtered.

I did add -stall arguement when running simics, and the load/store transactions seem correct.
Can anyone help with this issue?
Any comment is highly appreciated.

Fei

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