Re: [Gems-users] L2 banks in CMP protocol

[lya755@xxxxxxxxxxxxxxxxxxxx]

Thanks, Mike. I was trying to use Network_Files/NUCA_Procs-4_ProcsPerChip-
1_L2Banks-4_Memories-4.txt without any modification. However, when I run the 
tester, I got this error:

Creating event queue...
Creating event queue done
Creating system...
  Processors: 4
failed assertion 'atoi((string_split(varStr, ':')).c_str()) == 
g_endpoint_bandwidth' at fn void Topology::makeFileSpecified() in 
network/simple/Topology.C:540
failed assertion 'atoi((string_split(varStr, ':')).c_str()) == 
g_endpoint_bandwidth' at fn void Topology::makeFileSpecified() in 
network/simple/Topology.C:540
At this point you might want to attach a debug to the running and get to the
crash site; otherwise press enter to continue

Tracking down the error, I found that this is because in rubyconfig.defaults  
g_endpoint_bandwidth is set to be 10000 while in NUCA_Procs-4_ProcsPerChip-
1_L2Banks-4_Memories-4.txt, bw_unit is set to be 1000, and they are supposed 
to be the same in that assertion in Topology.C. So I changed their value to 
both1000. After this, I run the tester, this time it doesn't give me an error, 
instead in hang till this step:

Parsing command line arguments:
  g_PROCS_PER_CHIP: 1
  tracefile = little.trace
  debug start cycle = 1
Ruby Timing Mode
Warning: optimizations not enabled.
Creating event queue...
Creating event queue done
Creating system...
  Processors: 4

Please give me a hint as what is possibly wrong. BTW, I tried to use gdb to 
debug but it seems that debugging wasn't enabled even if I followed the steps 
on Debugging_Ruby_README.

Thanks a lot!!!

Lei
----- Original Message ----- 
From: "Mike Marty" <mikem@xxxxxxxxxxx>
To: "'Gems Users'" <gems-users@xxxxxxxxxxx>
Sent: Wednesday, October 04, 2006 10:48 PM
Subject: Re: [Gems-users] L2 banks in CMP protocol


> The latency is determined by the network topology and the latency/bandwidth
> of the links.
> 
> You can specify this manually using a FILE_SPECIFIED network to precisely
> specify the access latency of remote banks.
> 
> --Mike
> 
>> 
>> Dear List,
>> 
>> I am using MSI_MOSI_CMP_directory protocol and one question has been
>> bothering
>> me for a while. I've asked about this question before: Although in CMP
>> protocols, all processors share one L2 cache, this L2 cache can be divided
>> in
>> banks; so when adding L2 access latency does GEMS take into consideration
>> the
>> distance between the request processor and the respond L2 cache bank? The
>> answer I got from the list is: yes. But exactly how do we specify the
>> access
>> latency of L2 banks on one chip?
>> 
>> TIA!!
>> Lei
>> 
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