[Gems-users] L2 banks in CMP protocol

[lya755@xxxxxxxxxxxxxxxxxxxx]

Dear List,

I am using MSI_MOSI_CMP_directory protocol and one question has been bothering 
me for a while. I've asked about this question before: Although in CMP 
protocols, all processors share one L2 cache, this L2 cache can be divided in 
banks; so when adding L2 access latency does GEMS take into consideration the 
distance between the request processor and the respond L2 cache bank? The 
answer I got from the list is: yes. But exactly how do we specify the access 
latency of L2 banks on one chip?

TIA!!
Lei

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