Re: [Gems-users] interaction with cache controller

["Dave Z." <zhu_dave@xxxxxxxxx>]

Thanks for your reply. Let me revise my questions.

As I understand, Simics makes a call to makeRequest in
Sequencer.C when there is a cache request such as
load, store, atomic, etc. When/where does Simics make
such a call? In SimicsDriver.C or SimicsProcessor.C?
Please correct me if I'm wrong.

Also, does Ruby check the validity of an address it
receives from Simics? In other words, does it check to
see if the address is in the cache boundaries? If so,
could you please tell me where?

> Another approach would be to a ruby command that can
> be
> invoked from the Simics command line (similar to
> ruby0.clear-stats).
> Then you could setup a callback function for magic
> instructions
> (see Simics manual) that invokes that command.  The
> tricky part
> here is passing the argument through the magic
> instruction.
> (Presumably, you want to pass in a prefetch address
> or something.)

But I would like to get the cache controller involved
in this process. The cache controller behavior is
defined in *.sm file and generated at compile time. Is
it possible to define a transition in the cache
controller (*.sm file) based on a magic instruction
argument?

Thanks.





> > ----- Original Message ----
> > From: Dave Z. <zhu_dave@xxxxxxxxx>
> > To: gems Users <gems-users@xxxxxxxxxxx>
> > Sent: Thursday, October 5, 2006 10:25:06 AM
> > Subject: [Gems-users] interaction with cache
> controller
> >
> > Hello All,
> >
> > I would like to interact with Ruby's cache
> controller
> > dynamically. For example, by sending flags to the
> > cache controller so that it takes certain
> > actions/transitions. My main goal is to provide
> > prefetching hints from the program itself to the
> cache
> > controller. One way to establish interaction
> between
> > programs and Ruby is to use magic instructions,
> but I
> > believe this will not work in my case as magic
> > instructions are dynamic and the cache
> controller's
> > behavior is generated at compile time. Is there a
> way
> > to establish such interaction?
> >
> > Another way to modify the cache controller
> behavior at
> > run time could involve monitoring the address bus
> and
> > checking to see if certain registers/memory
> locations
> > have been accessed. Is it possible to monitor the
> > address bus and add this functionality to the
> cache
> > controller? If yes, can you give me a sense of how
> > much work is involved and where to start?
> >
> > Also, is it possible to access registers via Ruby
> or
> > should this be done at a lower level? Thank you
> very
> > much.
> >
> > Regards,
> >
> > Dave
> >
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