Re: [Gems-users] interaction with cache controller

[Greg Byrd <gbyrd@xxxxxxxx>]

Don't know what you mean by "observing the address bus," but the
cache model certainly sees every load/store address.  So if you can
do this through memory-mapped locations, it would be fairly easy
to look  for these addresses in the cache. 

Another approach would be to a ruby command that can be
invoked from the Simics command line (similar to ruby0.clear-stats).
Then you could setup a callback function for magic instructions
(see Simics manual) that invokes that command.  The tricky part
here is passing the argument through the magic instruction.
(Presumably, you want to pass in a prefetch address or something.)
Again, read the Simics documentation to learn how to do this -- it's
a Simics issue, not a GEMS issue.

Yes, you can read processor registers from Ruby, using the
Simics API.

I have no idea "how much work is involved,"  but you can start
by looking at the ruby/system/Sequencer.C code to see how memory
requests from the processor are relayed to the cache model.

...gb



Dave Z. wrote:
> Could you please help me with the following issues? Your help will be greatly appreciated.
>
> Regards,
>
> Dave
>
> ----- Original Message ----
> From: Dave Z. <zhu_dave@xxxxxxxxx>
> To: gems Users <gems-users@xxxxxxxxxxx>
> Sent: Thursday, October 5, 2006 10:25:06 AM
> Subject: [Gems-users] interaction with cache controller
>
> Hello All,
>
> I would like to interact with Ruby's cache controller
> dynamically. For example, by sending flags to the
> cache controller so that it takes certain
> actions/transitions. My main goal is to provide
> prefetching hints from the program itself to the cache
> controller. One way to establish interaction between
> programs and Ruby is to use magic instructions, but I
> believe this will not work in my case as magic
> instructions are dynamic and the cache controller's
> behavior is generated at compile time. Is there a way
> to establish such interaction?
>
> Another way to modify the cache controller behavior at
> run time could involve monitoring the address bus and
> checking to see if certain registers/memory locations
> have been accessed. Is it possible to monitor the
> address bus and add this functionality to the cache
> controller? If yes, can you give me a sense of how
> much work is involved and where to start?
>
> Also, is it possible to access registers via Ruby or
> should this be done at a lower level? Thank you very
> much.
>
> Regards,
>
> Dave
>
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