Many of the protocols do not actually profile the L1s.
In fact, the L1s are not separate entities in the all the protocols...
so the point at which L1 accesses are profiled varies from protocol to
protocol, if indeed they are profiled at all.
It should be relatively straightforward to add L1 profiling. If "fast
path hits" are ON, (see rubyconfig.defaults), then you can add profiling
code to Sequencer.C. Otherwise, you can use the L1 controller's SLICC code.
Regards,
Dan Gibson
Ranjith Subramanian wrote:
Hello,
I have a question about how cache misses are profiled in ruby. I start
simics, load a checkpoint which is essentially the prompt after a linux
boots up, load ruby and continue simulating for a few seconds and dump
ruby stats. I see that the L1 instruction and data caches aren't
accessed at all but the L2 cache is. All the misses reported for the L2
cache are demand misses. I'm not sure what I'm missing here.
Ranjith
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