[Gems-users] Cache miss profiling

[Ranjith Subramanian <ranji@xxxxxxxxxxxxx>]

Hello,
 I have a question about how cache misses are profiled in ruby. I start 
simics, load a checkpoint which is essentially the prompt after a linux 
boots up, load ruby and continue simulating for a few seconds and dump 
ruby stats. I see that the L1 instruction and data caches aren't 
accessed at all but the L2 cache is. All the misses reported for the L2 
cache are demand misses. I'm not sure what I'm missing here.
Ranjith