Re: [Gems-users] Opal's micro-architectural module

[Luke Yen <lyen@xxxxxxxxxxx>]

> first question,
> i want use Opal as a timing simulator/module worked with simics to verify/evaluate my micro-architectural innovations.
> if my goal processor module,which is multi-processor core in a chip and multi-threading and so on, is different from Opal's micro-architectural  module , can  i  change Opal's micro-architectural  module to my own processor module? is it possible? of course my own processor module is sparc v9-based.
>

   Opal currently supports one thread context per core.  In the future (no
timeline as of yet) we will be releasing a version of Opal which simulates
SMT, with multiple thread contexts per core.

   The current version of GEMS can simulate multiple cores on a chip using
the CMP cache coherence protcools.

>  secend,
> Opal doesn't use Simics' MAI interface so far. may opal do it in future? and  may it be usefull for my own micro-architectural module?
>

   No, we will not be converting Opal to the MAI interface.

  In theory, using MAI will allow you to get a timing module up more
quickly because you tell Simics when various pipeline stages happen and it will provide
the functionality for those events.  However you may want to turn off
Simics' functionality regarding memory operations and implement your own,
for example the LSQ and when stores commit in the system.

  Luke