Re: [Gems-users] TLB simulation

[Luke Yen <lyen@xxxxxxxxxxx>]

Hi:

   I have in fact run into the same problem, and luckily a solution is
present in the Simics forum.  One of the Virtutech engineers posted the
TLB module source code in our forum, and I have previously recompiled
with different params to do exactly as you want - to reduce TLB misses.
I have attached the source code in this email.

  To recompile the module:

   1) untar mmu.tar.gz into
   $GEMS_ROOT/simics/src/devices

   2) run this command inside $GEMS_ROOT/simics/x86-linux/lib:  (or
amd64-linux/lib)
   make cheetah+mmu    (or cheetah-mmu)

   3) To make clean those modules:
    make clean-cheetah+mmu   (or cheetah-mmu)

  Note that Solaris has its own OS-controlled TSB, and I have not modified
the Solaris source to increase the size of that software structure.  This
module only allows you to modify the hardware TLBs.

  Regards,
   Luke

On Sun, 20 Aug 2006, Philip Garcia wrote:

> That could run into an interesting problem.   On a TLB miss, the
> UltraSparc drops an exception and the OS handles the miss, and
> repopulates the TLB.  I'm not 100% sure how the OS does that (for my
> research I've been looking through the linux source code on some of
> it, but have been sidetracked on some other issues lately).  It might
> be possible to tell Simics there are a different number of entries,
> and then simics could inform the OS, but I'm not 100% sure.   One
> other problem would be the fact that you'd have to reboot the virtual
> machine for each different test, as the TLB is handled purely by
> software.   If you mange to get anything to work with this let us
> know.   Hopefully someone else here has dealt with this issue before.
>
> Phil
> On Aug 20, 2006, at 10:03 PM, arrvindh shriraman wrote:
>
> > Is it possible to vary the TLB size ( or attach own functional TLB
> > module) in Opal/Ruby for simulation purposes. I am quite confused
> > whether its possible to attach user TLB timing module.
> >
> > My understanding is that Simics emulates its own Spitfire-MMU class
> > for the SPARC and in a Solaris-Sparc system any change in TLB
> > require us to modify OS and Arch.
> >
> > eg: Lets say we are trying to emulate a larger TLB to reduce no of
> > TLB misses, since SIMICS is emulating its own spitfire TLB, even if
> > some entry is a hit in our timing system it could be a miss in
> > SIMICSs MMU at this point wont Opal deviate from Simics. What does
> > Opal do on d-TLB miss exception ? I took at look at d-tlb.C and pseq.C
> >
> > Do you Yahoo!?
> > Everyone is raving about the all-new Yahoo! Mail Beta.
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>
>

Attachment: mmu.tar.gz
Description: Binary data