| That could run into an interesting problem. On a TLB miss, the UltraSparc drops an exception and the OS handles the miss, and repopulates the TLB. I'm not 100% sure how the OS does that (for my research I've been looking through the linux source code on some of it, but have been sidetracked on some other issues lately). It might be possible to tell Simics there are a different number of entries, and then simics could inform the OS, but I'm not 100% sure. One other problem would be the fact that you'd have to reboot the virtual machine for each different test, as the TLB is handled purely by software. If you mange to get anything to work with this let us know. Hopefully someone else here has dealt with this issue before.
Phil On Aug 20, 2006, at 10:03 PM, arrvindh shriraman wrote: Is it possible to vary the TLB size ( or attach own functional TLB module) in Opal/Ruby for simulation purposes. I am quite confused whether its possible to attach user TLB timing module.
My understanding is that Simics emulates its own Spitfire-MMU class for the SPARC and in a Solaris-Sparc system any change in TLB require us to modify OS and Arch.
eg: Lets say we are trying to emulate a larger TLB to reduce no of TLB misses, since SIMICS is emulating its own spitfire TLB, even if some entry is a hit in our timing system it could be a miss in SIMICSs MMU at this point wont Opal deviate from Simics. What does Opal do on d-TLB miss exception ? I took at look at d-tlb.C and pseq.C
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