Re: [Gems-users] L1, L2 states in CMP

[Bradford Beckmann <beckmann@xxxxxxxxxxx>]

On Sat, 22 Apr 2006, Arrvindh Shriraman wrote:

> Hi Mike and Brad,
>
> I am kinda in a hurry, which prompted me to use your personal emails. I am
> sorry about that.
>
> When running in a CMP configuration. Is it possible to use a single
> controller for both L1 and L2 ?

Well there are multiple ways I can imagine doing this.  Utilizing a single
controller to control the states of multiple caches within an inclusive
hierarchy could be very complicated.  You would have to service multiple
mandatory queues and manage the separate L1 states of multiple L1 caches.

A slightly easier way would be to keep the L1 and L2 controllers separate,
but add functionality in the get_state and set_state functions to check
the state of a block in the other appropriate caches before returning or
setting the cache state.  This is somewhat similar to how the persistent
request table overrides the state of a block in the CMP_token protocol.
But be careful when trying to debug your protocol using the
PROTOCOL_DEBUG_TRACE.  Blocks will now change state without explicit
transitions.

You can imagine this working by the L2 controller changing the state of a
block and so then later the L1 controller's get_state and set_state
functions use a "magic" pointer to the L2 cacheMemory to determine what
state the L1 block is in.  You would need to add/hack these magic pointers
into the slicc specification file of the cache controllers.

Brad

>
> The reason I require this, is that in my protocol, I require to make a
> state change for a cache block in the L1 and the L2 appear atomic without
> any intervening memory operations. Hence I need one machine to change
> state of both L1 and L2, and make it happen instantaneously. The L2 is
> shared in my configuration. Are there any alternative solutions to this ?
> I wouldnt want to use a schedule_event on the L2's in port since another
> memory operation could arrive at the same instant and these two could get
> reordered in the global event queue.
>
> Thanks
> --
> Arrvindh Shriraman
> Computer Science Dept
> University of Rochester
> www.cs.rochester.edu/u/ashriram
>

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