I got a chance to look at the full trace and it appears that setting
COLLECTOR_HANDLES_OFF_CHIP_REQUESTS to false has uncovered a possible
deadlock issue with the L1 writeback virtual network. It would be
interesting if you could use the SLICC DEBUG statements,
"ruby0.debug-filter l", and find out what L2Cache bank is the destination
of the register message sent by the transition:
314898 0 2 L1CacheSend_Register_with_Owner_Tokens O>S
[0x30a840, line 0x30a840]
The registration of the Owner token never arrives at a L2 bank and
therefore the persistent getS request from L1Cache 3 is not being
satisfied. The system doesn't seem to be too highly contended. It would
be interesting to find out what the registration message is stalled.
Brad
On Fri, 7 Apr 2006, Bradford Beckmann wrote:
>
> Steve,
>
> It appears that you have the configuration variable
> "COLLECTOR_HANDLES_OFF_CHIP_REQUESTS" set to false. Is that correct?
>
> When running the MOESI_CMP_NUCA with the DNUCA cache block allocation
> policy, i.e. "g_NUCA_PREDICTOR_CONFIG == DNUCA", the
> "COLLECTOR_HANDLES_OFF_CHIP_REQUESTS" should be set to true as specified
> by http://www.cs.wisc.edu/gems/doc/wiki/moin.cgi/CMP-NUCA
>
> However, the persistent requests mechanism should prevent the deadlock.
> I'm curious to see what happens to "line 0x30a840" between cycle 314953
> and 400001.
>
> Brad
>
>
>
>
> On Fri, 7 Apr 2006, Steve Barrus wrote:
>
> > > Yes. You can filter on the address "line 0x30a840" using grep to save
> > > space. Eventually "0 3 L1Cache" should issued a "Request_Timeout".
> > > Please send us up to cycle 400001 but just for address "line 0x30a840".
> >
> > Here you go. Thanks.
> >
> > -Steve
> >
> > 314500 2 -1 Seq Begin > [0x30a840, line 0x30a840]
> > 314500 3 -1 Seq Begin > [0x30a840, line 0x30a840]
> > 314500 4 -1 Seq Begin > [0x30a840, line 0x30a840]
> > 314500 5 -1 Seq Begin > [0x30a840, line 0x30a840]
> > 314500 7 -1 Seq Begin > [0x30a840, line 0x30a840]
> > 314504 0 7 L1Cache Load NP>IS [0x30a840, line 0x30a840]
> > 314504 0 5 L1Cache Load NP>IS [0x30a840, line 0x30a840]
> > 314504 0 4 L1Cache Load NP>IS [0x30a840, line 0x30a840]
> > 314504 0 3 L1Cache Load NP>IS [0x30a840, line 0x30a840]
> > 314504 0 2 L1Cache Load NP>IS [0x30a840, line 0x30a840]
> > 314510 0 49 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314510 0 113 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314510 0 33 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314510 0 65 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314510 0 81 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314526 0 3 Collector Miss_Get_last Col_NP>Col_P [0x30a840, line 0x30a840]
> > 314526 0 5 Collector Miss_Get_last Col_NP>Col_P [0x30a840, line 0x30a840]
> > 314527 0 3 Collector Issue_L2_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314527 0 5 Collector Issue_L2_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314528 0 4 Collector Miss_Get_last Col_NP>Col_P [0x30a840, line 0x30a840]
> > 314529 0 4 Collector Issue_L2_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314530 0 7 Collector Miss_Get_last Col_NP>Col_P [0x30a840, line 0x30a840]
> > 314531 0 7 Collector Issue_L2_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314532 0 2 Collector Miss_Get_last Col_NP>Col_P [0x30a840, line 0x30a840]
> > 314533 0 2 Collector Issue_L2_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314536 0 241 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314536 0 241 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314538 0 241 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314538 0 145 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314538 0 145 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314538 0 129 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314538 0 129 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314538 0 17 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314540 0 241 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314540 0 17 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314540 0 129 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314540 0 145 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314542 0 17 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314542 0 129 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314542 0 145 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314542 0 241 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314544 0 145 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314544 0 129 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314544 0 17 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314550 0 225 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314550 0 225 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314550 0 5 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314550 0 3 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314552 0 225 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314552 0 4 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314554 0 225 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314554 0 3 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314554 0 3 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314554 0 5 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314554 0 5 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314554 0 5 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314554 0 7 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314556 0 2 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314556 0 4 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314556 0 4 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314556 0 4 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314558 0 7 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314558 0 7 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314558 0 7 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314558 0 225 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314560 0 2 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314560 0 2 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314560 0 2 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314566 0 5 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314566 0 3 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314568 0 4 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314570 0 7 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314574 0 2 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314652 0 113 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314652 0 113 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314653 0 113 L2Cache L1_GETS L2_NP>L2_NP [0x30a840, line 0x30a840]
> > 314672 0 4 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314672 0 3 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314673 0 2 Collector Miss_Get Col_P>Col_P [0x30a840, line 0x30a840]
> > 314804 0 7 L1Cache Request_Timeout IS>IS [0x30a840, line 0x30a840]
> > 314804 0 5 L1Cache Request_Timeout IS>IS [0x30a840, line 0x30a840]
> > 314804 0 4 L1Cache Request_Timeout IS>IS [0x30a840, line 0x30a840]
> > 314804 0 2 L1Cache Request_Timeout IS>IS [0x30a840, line 0x30a840]
> > 314804 0 3 L1Cache Request_Timeout IS>IS [0x30a840, line 0x30a840]
> > 314808 0 4 L1Cache Own_Lock_or_Unlock IS>IS [0x30a840, line 0x30a840]
> > 314808 0 3 L1Cache Own_Lock_or_Unlock IS>IS [0x30a840, line 0x30a840]
> > 314808 0 2 L1Cache Own_Lock_or_Unlock IS>IS [0x30a840, line 0x30a840]
> > 314808 0 5 L1Cache Own_Lock_or_Unlock IS>IS [0x30a840, line 0x30a840]
> > 314808 0 7 L1Cache Own_Lock_or_Unlock IS>IS [0x30a840, line 0x30a840]
> > 314810 0 113 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314810 0 49 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314810 0 65 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314810 0 81 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314810 0 33 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314812 0 1 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314814 0 4 L1Cache Persistent_GETS IS>IS_L [0x30a840, line 0x30a840] L1Cache-3
> > 314814 0 6 L1Cache Persistent_GETS I_L>I_L [0x30a840, line 0x30a840]
> > 314814 0 1 L1Cache Persistent_GETS I_L>I_L [0x30a840, line 0x30a840]
> > 314814 0 3 L1Cache Own_Lock_or_Unlock IS>IS [0x30a840, line 0x30a840]
> > 314815 0 0 L1Cache Persistent_GETS MM>I_L [0x30a840, line 0x30a840] L1Cache-7
> > 314816 0 97 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314816 0 5 L1Cache Persistent_GETS IS>IS_L [0x30a840, line 0x30a840] L1Cache-4
> > 314816 0 4 L1Cache Persistent_GETS IS_L>IS_L [0x30a840, line 0x30a840]
> > 314816 0 2 L1Cache Own_Lock_or_Unlock IS>IS [0x30a840, line 0x30a840]
> > 314816 0 6 L1Cache Persistent_GETS I_L>I_L [0x30a840, line 0x30a840]
> > 314816 0 193 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314816 0 3 L1Cache Persistent_GETS IS>IS_L [0x30a840, line 0x30a840] L1Cache-2
> > 314818 0 33 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314818 0 193 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314818 0 241 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314818 0 225 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314818 0 17 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314819 0 145 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314819 0 129 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314821 0 129 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314821 0 145 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314822 0 3 L1Cache Persistent_GETS IS_L>IS_L [0x30a840, line 0x30a840]
> > 314822 0 1 L1Cache Persistent_GETS I_L>I_L [0x30a840, line 0x30a840]
> > 314822 0 6 L1Cache Persistent_GETS I_L>I_L [0x30a840, line 0x30a840]
> > 314822 0 5 L1Cache Persistent_GETS IS_L>IS_L [0x30a840, line 0x30a840]
> > 314822 0 5 L1Cache Persistent_GETS IS_L>IS_L [0x30a840, line 0x30a840]
> > 314822 0 2 L1Cache Own_Lock_or_Unlock IS>IS [0x30a840, line 0x30a840]
> > 314822 0 97 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314822 0 4 L1Cache Persistent_GETS IS_L>IS_L [0x30a840, line 0x30a840]
> > 314824 0 241 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314824 0 7 L1Cache Persistent_GETS IS>IS_L [0x30a840, line 0x30a840] L1Cache-5
> > 314824 0 113 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314824 0 6 L1Cache Persistent_GETS I_L>I_L [0x30a840, line 0x30a840]
> > 314825 0 1 L1Cache Persistent_GETS I_L>I_L [0x30a840, line 0x30a840]
> > 314825 0 2 L1Cache Own_Lock_or_Unlock IS>IS [0x30a840, line 0x30a840]
> > 314825 0 145 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314825 0 129 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314826 0 241 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314826 7 -1 Seq Done > [0x30a850, line 0x30a840] 326 cycles L1Cache_wCC No
> > 314826 0 7 L1Cache Data_All_Tokens IS_L>M_W [0x30a840, line 0x30a840] L1Cache-0
> > 314826 0 3 Collector Deallocate_Entry Col_P>Col_NP [0x30a840, line 0x30a840]
> > 314826 0 5 Collector Deallocate_Entry Col_P>Col_NP [0x30a840, line 0x30a840]
> > 314828 0 7 L1Cache Persistent_GETS M_W>M_W [0x30a840, line 0x30a840]
> > 314828 0 3 L1Cache Persistent_GETS IS_L>IS_L [0x30a840, line 0x30a840]
> > 314828 0 4 Collector Deallocate_Entry Col_P>Col_NP [0x30a840, line 0x30a840]
> > 314829 0 145 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314829 0 129 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314829 0 17 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314830 0 4 L1Cache Persistent_GETS IS_L>IS_L [0x30a840, line 0x30a840]
> > 314830 0 17 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314830 0 7 L1Cache Persistent_GETS M_W>M_W [0x30a840, line 0x30a840]
> > 314830 0 7 Collector Deallocate_Entry Col_P>Col_NP [0x30a840, line 0x30a840]
> > 314830 0 2 L1Cache Own_Lock_or_Unlock IS>IS [0x30a840, line 0x30a840]
> > 314831 0 1 L1Cache Persistent_GETS I_L>I_L [0x30a840, line 0x30a840]
> > 314831 0 5 L1Cache Persistent_GETS IS_L>IS_L [0x30a840, line 0x30a840]
> > 314832 0 113 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314832 0 7 L1Cache Persistent_GETS M_W>M_W [0x30a840, line 0x30a840]
> > 314832 0 2 Collector Deallocate_Entry Col_P>Col_NP [0x30a840, line 0x30a840]
> > 314833 0 113 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314833 0 129 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314833 0 145 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314835 0 17 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314836 0 6 L1Cache Persistent_GETS I_L>I_L [0x30a840, line 0x30a840]
> > 314837 0 1 L1Cache Persistent_GETS I_L>I_L [0x30a840, line 0x30a840]
> > 314839 0 0 L1Cache Persistent_GETS I_L>I_L [0x30a840, line 0x30a840]
> > 314851 0 0 L1Cache Persistent_GETS I_L>I_L [0x30a840, line 0x30a840]
> > 314852 0 1 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314858 0 1 Directory Lockdown NO>L [0x30a840, line 0x30a840] L1Cache-7
> > 314858 0 1 Directory Lockdown L>L [0x30a840, line 0x30a840]
> > 314858 0 1 Directory Lockdown L>L [0x30a840, line 0x30a840]
> > 314860 0 1 Directory Lockdown L>L [0x30a840, line 0x30a840]
> > 314860 0 1 Directory Lockdown L>L [0x30a840, line 0x30a840]
> > 314860 0 0 L1Cache Persistent_GETS I_L>I_L [0x30a840, line 0x30a840]
> > 314865 0 0 L1Cache Persistent_GETS I_L>I_L [0x30a840, line 0x30a840]
> > 314876 0 7 L1Cache Use_TimeoutStarverS M_W>S_L [0x30a840, line 0x30a840] L1Cache-2
> > 314877 0 1 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314880 0 7 L1Cache Persistent_GETS S_L>S_L [0x30a840, line 0x30a840]
> > 314882 0 113 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314884 0 1 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314886 0 0 L1Cache Persistent_GETS I_L>I_L [0x30a840, line 0x30a840]
> > 314888 0 6 L1Cache Persistent_GETS I_L>I_L [0x30a840, line 0x30a840]
> > 314890 0 145 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314890 0 129 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314894 0 5 L1Cache Persistent_GETS IS_L>IS_L [0x30a840, line 0x30a840]
> > 314897 2 -1 Seq Done > [0x30a850, line 0x30a840] 397 cycles L1Cache_wCC No
> > 314897 0 2 L1Cache Data_Owner IS>O [0x30a840, line 0x30a840] L1Cache-7
> > 314898 0 2 L1CacheSend_Register_with_Owner_Tokens O>S [0x30a840, line 0x30a840]
> > 314900 0 3 L1Cache Persistent_GETS IS_L>IS_L [0x30a840, line 0x30a840]
> > 314900 0 17 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314900 0 2 L1Cache Own_Lock_or_Unlock S>S [0x30a840, line 0x30a840]
> > 314901 0 2 L1Cache Persistent_GETS S>S_L [0x30a840, line 0x30a840] L1Cache-3
> > 314902 0 4 L1Cache Persistent_GETS IS_L>IS_L [0x30a840, line 0x30a840]
> > 314902 0 1 L1Cache Persistent_GETS I_L>I_L [0x30a840, line 0x30a840]
> > 314903 0 33 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314908 0 1 L1Cache Persistent_GETS I_L>I_L [0x30a840, line 0x30a840]
> > 314909 0 3 L1Cache Own_Lock_or_Unlock IS_L>IS [0x30a840, line 0x30a840]
> > 314912 0 17 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314914 0 3 L1Cache Ack IS>IS [0x30a840, line 0x30a840]
> > 314915 0 4 L1Cache Persistent_GETS IS_L>IS_L [0x30a840, line 0x30a840]
> > 314915 0 129 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314915 0 145 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314917 0 113 L2Cache Persistent_GETS L2_I_L>L2_I_L [0x30a840, line 0x30a840]
> > 314919 0 7 L1Cache Persistent_GETS S_L>S_L [0x30a840, line 0x30a840]
> > 314924 0 5 L1Cache Persistent_GETS IS_L>IS_L [0x30a840, line 0x30a840]
> > 314927 0 6 L1Cache Persistent_GETS I_L>I_L [0x30a840, line 0x30a840]
> > 314930 0 1 Directory Lockdown L>L [0x30a840, line 0x30a840]
> > 314945 0 0 L1Cache Persistent_GETS I_L>I_L [0x30a840, line 0x30a840]
> > 314953 0 1 Directory Lockdown L>L [0x30a840, line 0x30a840]
> >
> > _______________________________________________
> > Gems-users mailing list
> > Gems-users@xxxxxxxxxxx
> > https://lists.cs.wisc.edu/mailman/listinfo/gems-users
> >
>
> -----------------------------------------------------------------
> Department of Computer Science Residence
> University of Wisconsin
> 1210 W. Dayton St. #6366 608 Eagle Heights Apt. L
> Madison, WI 53706 Madison, WI 53705
> (608)265-2702 (608)852-6133
> -----------------------------------------------------------------
>
-----------------------------------------------------------------
Department of Computer Science Residence
University of Wisconsin
1210 W. Dayton St. #6366 608 Eagle Heights Apt. L
Madison, WI 53706 Madison, WI 53705
(608)265-2702 (608)852-6133
-----------------------------------------------------------------
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