Re: [Gems-users] Multi-line cache states

[Bradford Beckmann <beckmann@xxxxxxxxxxx>]

Arrvindh,

First off, what hardware are you envisioning to do this?  I have heard of
circuits flash clearing bits in multiple cache blocks, but I have never
heard of a circuit atomically changing multiple cache block states.

Secondly, it is not straight forward to do this in SLICC.  Many SLICC &
Ruby Eventqueue design decisions have been made assuming that all state
changes are atomic on the per block basis.  However, I do have experience
of once trying to change two cache state transitions using a SLICC hack I
called 'doubleTrigger'.  Basically one event from an inport triggered two
state changes.  However, to make this work, you need to go through some
complicated checking to ensure the second transition will not be stalled
before you allow the first transition to occur.  I found this code
complicated and difficult to maintain.  I don't recommend doing it.

Another way to implement it would be through local variables in the cache
controller and cache block timestamps.  Then override the cache state
stored in CacheMemory similar to how a TBE entry can.  However this way
may not be much easier or less complicated.

Brad



On Mon, 17 Oct 2005, arrvindh shriraman wrote:

> Hi,
>
> Is it possible to change the states of multiple
> cache-lines with a single event ? Can all lines be
> changed atomically.
>
> For eg: Lets say that with a event PrRd to address
> 0x0a00 I want to downgrade all 'M' to 'S' lines. This
> should happen atomically.
>
>
> Thanks,
>
> Arrvindh Shriraman
> Conputer Science Department
> University of Rochester
>
>
>
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