Date: | Sun, 23 Feb 2025 14:51:27 -0800 |
---|---|
From: | wxrdnx <noreply@xxxxxxxxxx> |
Subject: | [DynInst_API:] [dyninst/dyninst] 65dc01: Fix isReturn bug |
Branch: refs/heads/angushe/riscv Home: https://github.com/dyninst/dyninst Commit: 65dc0185ef48f20b4583706e866ed8670231be3f https://github.com/dyninst/dyninst/commit/65dc0185ef48f20b4583706e866ed8670231be3f Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx> Date: 2025-02-23 (Sun, 23 Feb 2025) Changed paths: M instructionAPI/src/Instruction.C M parseAPI/src/IA_riscv64.C Log Message: ----------- Fix isReturn bug To unsubscribe from these emails, change your notification settings at https://github.com/dyninst/dyninst/settings/notifications |
[← Prev in Thread] | Current Thread | [Next in Thread→] |
---|---|---|
|
Previous by Date: | [DynInst_API:] [dyninst/dyninst] 8de35c: Revert wrong readRegister fix, wxrdnx |
---|---|
Next by Date: | [DynInst_API:] [dyninst/dyninst] ba803e: Fix rose handling of arm instructions (#1895), bbiiggppiigg |
Previous by Thread: | [DynInst_API:] [dyninst/dyninst] 65bc63: Add conditional branch, wxrdnx |
Next by Thread: | [DynInst_API:] [dyninst/dyninst] 661884: Rewrite shifts and constants in RISC-V codegen, wxrdnx |
Indexes: | [Date] [Thread] |