Date: | Sun, 02 Feb 2025 16:40:35 -0800 |
---|---|
From: | wxrdnx <noreply@xxxxxxxxxx> |
Subject: | [DynInst_API:] [dyninst/dyninst] 49ca93: Rewrite load and store using I-Type and S-Type gen... |
Branch: refs/heads/angushe/riscv Home: https://github.com/dyninst/dyninst Commit: 49ca9375ba8fe8a5945e7b72d64d0dc2b05aefd9 https://github.com/dyninst/dyninst/commit/49ca9375ba8fe8a5945e7b72d64d0dc2b05aefd9 Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx> Date: 2025-02-02 (Sun, 02 Feb 2025) Changed paths: M common/src/arch-riscv64.h M dyninstAPI/src/codegen-riscv64.C M dyninstAPI/src/codegen-riscv64.h Log Message: ----------- Rewrite load and store using I-Type and S-Type generator Commit: dba9ebb40419bd4711066675d4f444333c9373a8 https://github.com/dyninst/dyninst/commit/dba9ebb40419bd4711066675d4f444333c9373a8 Author: wxrdnx <wxrdnx@xxxxxxxxxxxxxx> Date: 2025-02-02 (Sun, 02 Feb 2025) Changed paths: M common/src/arch-riscv64.h M dyninstAPI/src/codegen-riscv64.C M dyninstAPI/src/codegen-riscv64.h M dyninstAPI/src/emit-riscv64.C Log Message: ----------- Finish emit basic operators Compare: https://github.com/dyninst/dyninst/compare/1cbe905f4b96...dba9ebb40419 To unsubscribe from these emails, change your notification settings at https://github.com/dyninst/dyninst/settings/notifications |
[← Prev in Thread] | Current Thread | [Next in Thread→] |
---|---|---|
|
Previous by Date: | [DynInst_API:] [dyninst/dyninst] 1cbe90: Fix wrong indexing order in INSN_SET, wxrdnx |
---|---|
Next by Date: | [DynInst_API:] [dyninst/dyninst] 121e8a: Add test skeleton, Tim Haines |
Previous by Thread: | [DynInst_API:] [dyninst/dyninst] 49871f: initial commit that compiles, bbiiggppiigg |
Next by Thread: | [DynInst_API:] [dyninst/dyninst] 4a222d: Make pstate flags 1 bit, Tim Haines |
Indexes: | [Date] [Thread] |