[DynInst_API:] [dyninst/dyninst] 1af4ed: Fix Register handling for AMDGPU

[bbiiggppiigg <noreply@xxxxxxxxxx>]

  Branch: refs/heads/bbiiggppiigg/refactor-amdgpu-register-handling
  Home:   https://github.com/dyninst/dyninst
  Commit: 1af4edc8ad0fb0569572a53acc8640525c197952
      https://github.com/dyninst/dyninst/commit/1af4edc8ad0fb0569572a53acc8640525c197952
  Author: wuxx1279 <bbiiggppiigg@xxxxxxxxx>
  Date:   2025-01-27 (Mon, 27 Jan 2025)

  Changed paths:
    M common/h/registers/AMDGPU/amdgpu_gfx908_regs.h
    M common/h/registers/AMDGPU/amdgpu_gfx90a_regs.h
    M common/h/registers/AMDGPU/amdgpu_gfx940_regs.h
    M dataflowAPI/rose/registers/amdgpu.h
    M dataflowAPI/rose/semantics/Registers.C
    M dataflowAPI/rose/semantics/SymEvalSemantics.C
    M external/rose/amdgpuInstructionEnum.h

  Log Message:
  -----------
  Fix Register handling for AMDGPU

1. Unify register definitions for GFX908 with 90A and 940
  a. Separate WAITCNT into a separate register class
  b. Move SCC into MISC class
  c. Fix wrong index number for hw_reg_ib_sts
2. Update rose AMDGPU enum to reflect the relavnt changes
  a. Each MISC type register should have a minor enum value matching
  its index number
3. Update the register descriptor creation logic casting the index
4. Update the register conversion logic in rose
  a. Remove the case for hardware register as scc is moved to MISC
  b. Add the case for handling the MISC registers



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