[DynInst_API:] [dyninst/dyninst] a85835: Add Support for AMDGPU CDNA2 Architectures based o...

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  Branch: refs/heads/master
  Home:   https://github.com/dyninst/dyninst
  Commit: a85835269188c24a5c27a50bbd06751c1badc3d7
      https://github.com/dyninst/dyninst/commit/a85835269188c24a5c27a50bbd06751c1badc3d7
  Author: bbiiggppiigg <bbiiggppiigg@xxxxxxxxx>
  Date:   2022-02-23 (Wed, 23 Feb 2022)

  Changed paths:
    A common/h/AMDGPU/cdna2/amdgpu_cdna2_sys_regs.h
    A common/h/amdgpu_cdna2_op_table.h
    A common/h/amdgpu_cdna2_sys_regs.h
    A common/h/amdgpu_cdna_op_table.h
    A common/h/amdgpu_cdna_sys_regs.h
    M common/h/amdgpu_op_table.h
    M common/h/dyn_regs.h
    M common/h/entryIDs.h
    M common/src/dyn_regs.C
    M dwarf/src/dwarfHandle.C
    M elf/src/Elf_X.C
    M instructionAPI/CMakeLists.txt
    M instructionAPI/h/Instruction.h
    M instructionAPI/h/Operation_impl.h
    M instructionAPI/h/Result.h
    A instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C
    A instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.h
    A instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.C
    A instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_decoder_impl.h
    A instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_insn_entry.h
    A instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_op_table.h
    A instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_opcode_tables.C
    A instructionAPI/src/AMDGPU/cdna2/amdgpu_cdna2_sys_regs.h
    A instructionAPI/src/AMDGPU/cdna2/decodeOperands.C
    A instructionAPI/src/AMDGPU/cdna2/decodeOperands.h
    A instructionAPI/src/AMDGPU/cdna2/finalizeOperands.C
    A instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C
    A instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.h
    A instructionAPI/src/AMDGPU/vega/amdgpu_vega_decoder_impl.C
    A instructionAPI/src/AMDGPU/vega/amdgpu_vega_decoder_impl.h
    A instructionAPI/src/AMDGPU/vega/amdgpu_vega_insn_entry.h
    A instructionAPI/src/AMDGPU/vega/amdgpu_vega_opcode_tables.C
    M instructionAPI/src/Instruction.C
    M instructionAPI/src/InstructionCategories.C
    R instructionAPI/src/InstructionDecoder-amdgpu-vega.C
    R instructionAPI/src/InstructionDecoder-amdgpu-vega.h
    M instructionAPI/src/InstructionDecoderImpl.C
    M instructionAPI/src/Operand.C
    M instructionAPI/src/Operation.C
    M instructionAPI/src/Register.C
    M instructionAPI/src/amdgpu_branchinsn_table.h
    R instructionAPI/src/amdgpu_decoder_impl_vega.C
    R instructionAPI/src/amdgpu_decoder_impl_vega.h
    R instructionAPI/src/amdgpu_insn_entry.h
    R instructionAPI/src/amdgpu_opcode_tables.C
    M parseAPI/src/IA_IAPI.C
    M parseAPI/src/IA_amdgpu.C
    M parseAPI/src/SymbolicExpression.C
    M proccontrol/src/process.C

  Log Message:
  -----------
  Add Support for AMDGPU CDNA2 Architectures based on XML ISA spec (#1107)

Add Initial Support for cdna based on the lastest version of XML file ( 20210720 )

Added new register names based on the latest xml-isa drop

Decoder implementation updated based on the latest xml-isa drop

renumbered registers to make low registers have the same value as full register (or its super set)

add larger memoery types for representing consecutive registers used as a single operand

Modify the format function to output multiple registers as a single operand correctly, handling for certain registers are still being worked on

split register-vector into multiple registers