[DynInst_API:] [dyninst/dyninst] 3fae9d: Nvidia GPU slicing and support for opening Intel G...

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  Branch: refs/heads/master
  Home:   https://github.com/dyninst/dyninst
  Commit: 3fae9d977e7b48b366d3af0ce5cf8ff747e568bb
      https://github.com/dyninst/dyninst/commit/3fae9d977e7b48b366d3af0ce5cf8ff747e568bb
  Author: Xiaozhu Meng <mxz297@xxxxxxxxx>
  Date:   2020-09-28 (Mon, 28 Sep 2020)

  Changed paths:
    M common/h/dyn_regs.h
    M common/h/entryIDs.h
    M common/src/dyn_regs.C
    M dataflowAPI/h/Absloc.h
    M dataflowAPI/h/AbslocInterface.h
    M dataflowAPI/h/slicing.h
    M dataflowAPI/src/Absloc.C
    M dataflowAPI/src/AbslocInterface.C
    M dataflowAPI/src/slicing.C
    M dwarf/src/dwarfHandle.C
    M elf/h/Elf_X.h
    M elf/src/Elf_X.C
    M instructionAPI/h/Instruction.h
    M instructionAPI/h/Operand.h
    M instructionAPI/src/Instruction.C
    M instructionAPI/src/Operand.C
    M parseAPI/src/JumpTableFormatPred.h
    M parseAPI/src/JumpTableIndexPred.h

  Log Message:
  -----------
  Nvidia GPU slicing and support for opening Intel GPU binaries (#865)

* Add cuda registers and ops

* Make appendOperand available to external usage

* Add cuda register size (>=sm_50)

* Refactor slicing to use Block::getInsns to get instructions inside a basic block

* Add a placeholder for pc on cuda and remove a few asserts

* Not decode cuda instructions

* Fix register naming bug

* Change constant to 500 to find more dependencies

* Remove slicing constraint

* Add an interface to use external AssignmentConverter for Slicing

* Add support to share instruction cache between different slices

* Adding predicates fields to Operand classes

* Add predicate registers and methods to get predicate registers

* Add barrier registers

* Initial implementation of slicing support for predicated instructions

* Add missed code for copy predicate information in Operand class's copy constructor and equal operator

* Comment logs

* Add Turing registers

* Fix reg prefix

* added support for intel gen9 gpu

* Remove tab and logs

* Add support for intel gpu instructions

* Add slicing size limit factor

* 1. Avoid using Block pointer as key to a cache. Use block start address
2. Change the default value of bound size limit factor
3. Changes to suppress warning regarding to intel gpu
4. Other code cleanup

Co-authored-by: Jokeren <robinho364@xxxxxxxxx>
Co-authored-by: Aaron Cherian <aarontcopal2@xxxxxxxxxxxxxxxxxxxxxxxxxxx>