[DynInst_API:] [dyninst/dyninst] 243617: Added/updated support for 271 new power instructio...

[Benjamin Welton <welton@xxxxxxxxxxx>]

  Branch: refs/heads/master
  Home:   https://github.com/dyninst/dyninst
  Commit: 243617adebfaa47e5bd27b19648ecc8145de9e9d
      https://github.com/dyninst/dyninst/commit/243617adebfaa47e5bd27b19648ecc8145de9e9d
  Author: Benjamin Welton <welton@xxxxxxxxxxx>
  Date:   2018-11-05 (Mon, 05 Nov 2018)

  Changed paths:
    M common/h/entryIDs.h
    M instructionAPI/src/InstructionDecoder-power.C
    M instructionAPI/src/InstructionDecoder-power.h
    M instructionAPI/src/power_opcode_tables.C

  Log Message:
  -----------
  Added/updated support for 271 new power instructions

Added full/partial support for the following instructions:

vsldoi ,maddhd ,maddhdu ,maddld ,vbpermq ,extended ,bcdctsq ,bcdcfsq ,bcdctz ,bcdctn ,bcdcfz ,bcdcfn ,bcdsetsgn ,vclzlsbb ,vctzlsbb ,vnegw ,vnegd ,vprtybw ,vprtybd ,vprtybq ,vextsb2w ,vextsh2w ,vextsb2d ,vextsh2d ,vextsw2d ,vctzb ,vctzh ,vctzw ,vctzd ,dcbst ,wait ,td ,lxsiwax ,stfpdux ,slbiag ,cmpeqb ,cmprb ,cnttzw ,cnttzd ,cp_abort ,darn ,extswsl ,ldat ,lwat ,mcrxrx ,mfvsrld ,modsd ,modud ,modsw ,moduw ,msgsnd ,msgclr ,msgsndp ,msgclrp ,msgsync ,mtvsrdd ,mfvsrwz ,mtvsrd ,mtvsrwa ,mtvsrwz ,mtvsrws ,setb ,slbieg ,slbsync ,stdat ,stwat ,clrbhrb ,mfbhrbe ,icbt ,lqarx ,stqcx ,tbegin ,tend ,tabort ,tabortwc ,tabortwci ,tabortdc ,tabortdci ,tsr ,tcheck ,treclaim ,trechkpt ,addg6s ,cdtbcd ,cbcdtd ,divde ,divdeu ,modsd ,lbarx ,lharx ,ldbrx ,stbcx ,stdbrx ,sthcx ,lbzcix ,lwzcix ,ldcix ,stbcix ,sthcix ,stwcix ,stdcix ,lfdpx ,stfdpx ,prtyd ,prtyw ,slbfee ,slbfee ,slbmfee ,slbmfev ,mfocrf ,isel ,tlbiel ,slbmte ,subfze ,mtmsrd ,mtmsr ,copy ,paste ,extswsli ,stxvb16x ,wait ,lxsiwax ,mfvsr!
 d ,bpermd
 ,divwe ,divweu ,lfiwzx ,cmpb ,lfiwax ,lhzcix ,slbia ,slbie ,dtstsfi ,dcffix ,fcfids ,fcfidus ,dadd ,dcmpo ,dcmpu ,dctdp ,dctfix ,ddedpd ,ddiv ,denbcd ,diex ,dmul ,dquai ,dqua ,drintn ,drintx ,drrnd ,drsp ,dscli ,dscri ,dsub ,dtstdc ,dtstdg ,dtstex ,dtstsf ,frsqrtes ,dxex ,xxpermdi ,xvtdivsp ,xxsel ,xxsldwi ,xvnmaddasp ,xscmpexpdp ,xscvuxddp ,xxspltib ,xsaddsp ,xsmaddadp ,xsrdpi ,xssubdp ,xsmsubmdp ,xscmpexpdp ,xscmpexpdp ,xvrspip ,xxinsertw ,xvcmpeqdp ,xvrsqrtedp ,xxlor ,xsnmaddadp ,xscvdpuxds ,xvnabssp ,xvnegsp ,xvcvsxddp ,xsnmsubqp ,daddq ,dcffixq ,dcmpoq ,dcmpuq ,dctfixq ,dctqpq ,ddedpdq ,denbcdq ,ddivq ,diexq ,dmulq ,dquaiq ,dquaq ,drdpq ,drintnq ,drintxq ,drrndq ,dscliq ,dscriq ,dsubq ,dtstdcq ,dtstdgq ,dtstexq ,dtstsfq ,dxexq ,fcpsgn ,fre ,frim ,frin ,frip ,friz ,fctidz ,xsxexpdp ,xsxsigdp ,xscvdphp ,xscvhphp ,xvxexpdp ,xvxsigdp ,xxbrh ,xvxexpsp ,xvxsigsp ,xxbrw ,xxbrd ,xvcvhpsp ,xvcvsphp ,xxbrq ,xsxexpdp ,xvxexpdp ,xscvqpsdz ,dtstsfiq ,xscpsgnqp ,xsdivqp ,xsrqpxp ,fm!
 rgew
 ,fmrgow ,fcfidu, fctidu ,fctiduz ,fctiwu ,fctiwuz ,ftdiv ,ftsqrt ,mffs ,mffsce ,mffscdrn ,mffscdrn ,mffscdrni ,mffscrn ,mffsl ,xsabsqp ,xsxexpqp ,xsnegqp ,xsxsigqp ,xssqrtqp ,xsnabsqp ,xscvqpuwz ,xscvudqp ,xscvqpswz ,xscvsdqp ,xscvqpudz ,xscvqpdp ,xscvdpqp ,xscvqpsdz

Currently missing is operand decoding for the following operand types:

UIM(), BHRBE(), IH(), SP(), S(), TE(), DGM(), DCM(), CT(), RSP(), RTP(), EH(), PRS(), A(), R(), BC(), RC(), RIC(), SIM(), DCMX(), RO(), RMC(), EX(), SHB(), PS(), CY(), DRM(), SHW(), XC(), DM(), IMM8()

If an instruction with one of these operands is encounted, the operand will not be docoded and a warning message printed. Over time support for these operands will be added.



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