[DynInst_API:] [dyninst/dyninst] 6cbe57: 09/25

[Yuhan Xie <yxie@xxxxxxxxxxxxxxxxxxxx>]

  Branch: refs/heads/power_vector
  Home:   https://github.com/dyninst/dyninst
  Commit: 6cbe5730b72f7d67bf9e2b69a0709ea8c0266eca
      https://github.com/dyninst/dyninst/commit/6cbe5730b72f7d67bf9e2b69a0709ea8c0266eca
  Author: Yuhan Xie <yxie@xxxxxxxxxxxxxxxxxxxx>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M common/h/entryIDs.h
    M instructionAPI/src/power_opcode_tables.C

  Log Message:
  -----------
  09/25

p492-523(not including p523)
skipped: lxv (P492, new keyword DQ; TX not at the last bit),
   lxvx (P492, a slash in the memory map and two numbers are included)
	 stxsd (P498, new keyword VRS, stands for VSR[VSR+32].dword[0])
	 stxssp (P501, VRS)
	 stxv (P507, new keyword DQ)
	 xsabsqp (P512, 0 in it)

new keywords included:

	-included new keywords "XS", it should be the storing version of "XT")
	-included XA, XB (page 512 of manual, using the same pattern as RA, RB but XA and XB are for VSR, and there are AX & BX bits at the end of the instruction)
	-included VRA, VRB (page 520 of manual)

Additional:
--xsaddqp and xsaddqpo are sharing the same opcode, treated it as frsp and frsp.(page 520 of manual)


  Commit: 5af9ea93fd66ebbfe9ff4945489a32a21e1c97a6
      https://github.com/dyninst/dyninst/commit/5af9ea93fd66ebbfe9ff4945489a32a21e1c97a6
  Author: Yuhan Xie <yxie@xxxxxxxxxxxxxxxxxxxx>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Log Message:
  -----------
  Merge branch 'power_vector' of github.com:dyninst/dyninst into power_vector


  Commit: 2c8113207782d5f032271773403e78be0e977bde
      https://github.com/dyninst/dyninst/commit/2c8113207782d5f032271773403e78be0e977bde
  Author: Yuhan Xie <yxie@xxxxxxxxxxxxxxxxxxxx>
  Date:   2018-09-25 (Tue, 25 Sep 2018)

  Changed paths:
    M instructionAPI/src/power_opcode_tables.C

  Log Message:
  -----------
  09/25

p492-523(not including p523)
skipped: lxv (P492, new keyword DQ; TX not at the last bit),
   lxvx (P492, a slash in the memory map and two numbers are included)
				 stxsd (P498, new keyword VRS, stands for VSR[VSR+32].dword[0])
				 stxssp (P501, VRS)
				 stxv (P507, new keyword DQ)
				 xsabsqp (P512, 0 in it)

new keywords included:

	-included new keywords "XS", it should be the storing version of "XT")
	-included XA, XB (page 512 of manual, using the same pattern as RA, RB but XA and XB are for VSR, and there are AX & BX bits at the end of the instruction)
	-included VRA, VRB (page 520 of manual)

Additional:
--xsaddqp and xsaddqpo are sharing the same opcode, treated it as frsp and frsp.(page 520 of manual)


Compare: https://github.com/dyninst/dyninst/compare/1d4fc85ec0ff...2c8113207782
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