[DynInst_API:] [dyninst/dyninst] 3ac05a: Added semantics for the following instructions:


Date: Fri, 09 Sep 2016 09:33:19 -0700
From: Sunny Shah <shah28@xxxxxxxx>
Subject: [DynInst_API:] [dyninst/dyninst] 3ac05a: Added semantics for the following instructions:
  Branch: refs/heads/arm64/feature/semantics
  Home:   https://github.com/dyninst/dyninst
  Commit: 3ac05a7597024895d504adcc2c74ec75d873f02a
      https://github.com/dyninst/dyninst/commit/3ac05a7597024895d504adcc2c74ec75d873f02a
  Author: Sunny Shah <shah28@xxxxxxxx>
  Date:   2016-09-09 (Fri, 09 Sep 2016)

  Changed paths:
    M dataflowAPI/rose/semantics/DispatcherARM64.C
    M dataflowAPI/rose/semantics/DispatcherARM64.h
    M dataflowAPI/rose/semantics/SymEvalSemantics.C
    M dataflowAPI/rose/semantics/SymEvalSemantics.h

  Log Message:
  -----------
  Added semantics for the following instructions:

* Immediate and register variants of LDR, LDRB, LDRH, LDRSB, LDRSH, LDRSW, STR, STRB, STRH
* Literal variants of LDR and LDRSW

The signatures of readMemory() and writeMemory() in SymEvalSemantics::StateARM64 and SymEvalSemantics::MemoryStateARM64 are modified to be able to pass in the read and write sizes.


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