SIGARCH-MSG: February 2004 Digest of SIGARCH Messages

["Doug Burger" <dburger@cs.utexas.edu>]

This is the February 2004 Digest of SIGARCH Messages (sigarch-feb04):

* International Conference on Supercomputing (ICS) Call for Papers
  http://graal.ens-lyon.fr/ICS04/
  Submitted by Liviu Iftode <iftode@cs.umd.edu>

* HOT Chips 16 Call for Contributions
  http://www.hotchips.org
  Submitted by Allen Baum <ajbaum@mipos2.intel.com>

* Call for Papers: First Workshop on Temperature-Aware Computer Systems (TACS-1)
  http://www.cs.virginia.edu/~skadron/tacs/
  Submitted by Kevin Skadron <skadron@cs.virginia.edu>

* VPW2 Call for Papers
  http://www.csl.cornell.edu/VPW2/
  Submitted by Martin Burtscher <burtscher@csl.cornell.edu>

* CGO 2004 Call for Participation
  March 20-24, 2004 in Palo Alto, California 
  http://www.cgo.org
  Submitted by Mike Smith <smith@eecs.harvard.edu>

* SCOPES 2004 Call for Papers
  http://www.scopes2004.org
  Submitted by Marianne Dalmolen <marianne@ace.nl>

* New papers published online by Computer Architecture Letters
  http://www.comp-arch-letters.org/2003paps.html
  Submitted by Kevin Skadron <skadron@cs.virginia.edu>

--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@acm.org

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Doug Burger			  Office:	       3.432 ACES
Assistant Professor		  Phone:	     512-471-9795
Department of Computer Sciences	  Assistant:	     512-232-7460
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* International Conference on Supercomputing (ICS) Call for Papers

                        ICS-2004  Call for Papers
          The 18th  International Conference on Supercomputing
                    St. Malo, France, June 26-July 1, 2004
                       http://ics04.irisa.fr


Sponsored by ACM/SIGARCH In cooperation with IRISA/INRIA and 
		Ecole Normale Superieure de Lyon

ICS is the first international forum for the presentation of research 
results in high-performance computing systems.  

Papers are solicited on all aspects of research, development, and
application of high-performance systems, including new experimental 
and commercial systems, architectures with fine and coarse grain 
parallelism, grid computing, novel infrastructures for the Internet, 
parallel network processors, parallel I/O and storage, autonomic 
computing, ubiquitous computing, embedded and power-aware computer 
architectures, operating systems and support software, restructuring 
and optimizing compilers, program development tools, high-performance 
Java, performance evaluation studies, numerical or non-numerical 
algorithms, and computationally challenging scientific and e-business 
applications.

Papers should not exceed 6,000 words, and must be submitted
electronically using the submission form available at
http://graal.ens-lyon.fr/ICS04.  Submissions must be in pdf or
postscript format.  Reviews will be available about April 7 to
allow the authors to provide rebuttals.

Researchers and practitioners are also invited to submit workshop 
and/or tutorial proposals to the ICS 2004 Workshop/Tutorial Chair, no
later than January 15, 2004.
 
For further information and future updates, please refer to the ICS'04 
web site at http://graal.ens-lyon.fr/ICS04/

Important Dates

February 23, 2004 	  	Abstract due
March 1, 2004 	 	        Paper submission deadline
April 7, 2004 		 	Author notification
May 6, 2004 	 	        Final Paper due

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* HOT Chips 16 Call for Contributions

CALL FOR CONTRIBUTIONS
Stanford University
Palo Alto, California
August 22-24, 2004

For the last 15 years, Hot Chips has been the leading conference on
high-performance microprocessors and related integrated circuits. The
conference is held once a year in August on the Stanford University
campus in the center of the world's electronics capital, Silicon
Valley. The emphasis this year, as in previous years, is on real
products and realizable technology.

Topics of interest for this year's conference include but are
not limited to:

* Microprocessors
* Systems-on-chip
* Embedded processors
* Digital signal processors
* Application-specific processors
* Network/security processors
* Graphics/Multimedia/Game processors
* Communication/networking chips
* Wireless LAN/Wireless WAN chips
* Reconfigurable chips/processors
* Low-power chips/dynamic power management
* Novel chips: quantum computing, microarray
* Reliability and design for test
* Compiler technology
* Operating system/chip interaction
* Advanced semiconductor process technology
* Advanced packaging technology

Presentations at HOT Chips are in the form of 30-minute talks.
Presentation slides will be published in the HOT Chips Proceedings.
Participants are not required to submit written papers, but a select
group will be invited to submit a paper for inclusion in a special
issue of IEEE Micro.

Submissions must consist of a title, extended abstract (two pages
maximum), and the presenter's contact information (name, affiliation,
job title, address, phone, fax, and email). Please indicate whether
you have submitted, intend to submit or have already presented or
published a similar or overlapping submission to another conference or
journal. Also indicate if you would like the submission to be held
confidential; we do our best to maintain confidentiality.

Submissions are evaluated by the Program Committee on the basis of the
performance of the device (or devices), degree of innovation, use of
advanced technology, potential market significance, and anticipated
interest to the audience. Research and software contributions will
be evaluated with similar criteria. Authors will be notified of the
status of their submission by the end of April, 2004.

Don't miss this chance to present your work to an audience of
engineers, computer architects, and computer system and device
researchers. Submissions must be received no later than March 15, 2004.

Please make your submissions in plain ascii text (in the message, not
as an attachment) to:

hotchips-submission@cva.stanford.edu

(Submissions containing figures may be submitted in pdf, but plain
ascii is preferred.)

For more information, see the Hot Chips 16 Web site at:
http://www.hotchips.org

Send questions to
hotchips@cva.stanford.edu
or contact the co-program chairs:
Prof. Bill Dally at hotchips@cva.stanford.edu, or
Keith Diefendorff at keithd@mac.com

Sponsored by the Technical Committee on Microprocessors and
Microcomputers of the IEEE Computer Society

See the HOT CHIPS 16 web page for updates: http://www.hotchips.org

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* Call for Papers: First Workshop on Temperature-Aware Computer Systems (TACS-1)

Held in conjunction with ISCA-31, Munich Germany, June 19-23, 2004
Workshop website: http://www.cs.virginia.edu/~skadron/tacs/

Theme:

Many analysts suggest that increasing power density and resulting
difficulties in managing on-chip temperatures are some of the most
urgent obstacles to continued scaling of VLSI systems within the next
five to ten years. Just as has been done before for power-aware
computing, "temperature-aware" computing must be approached not just
from the packaging and circuit-design communities, but also from the
processor- and systems- architecture communities. Many techniques for
managing operating temperature will use power-management techniques, but
possibly in different ways than for energy efficiency. There is growing
interest in cooling solutions from the processor- and
systems-architecture domains, as evidenced by recent work on fetch
throttling, dynamic voltage scaling, and process scheduling in response
to thermal stress; and some progress has been made on modeling
infrastructure for this kind of research. But research so far has only
scratched the surface of what is possible. 

This workshop will serve as a forum to explore a broad spectrum of
topics pertaining to temperature-aware computer architecture, for
researchers to exchange ideas and initiate collaborations, and will help
to establish temperature-aware computing as an important research topic
in its own right. 

Topics of Interest: 

Submissions are welcomed on any topic pertaining to temperature-aware
architecture, including but not limited to: 

     Modeling 
     Dynamic thermal management for the CPU and other system components 
     Circuit/architecture/OS cooperation 
     Scheduling techniques 
     Sensitivity of other metrics to operating temperature 
     Workload characterization 
     Application-specific thermal optimizations 
     New applications and sampling techniques for thermal studies 
     Interaction of thermal management, energy efficiency, and voltage
stability. 
     Interaction of thermal management with real-time requirements 

The paper should be in IEEE conference format and at most ten pages in
length including all figures, references, etc.  Excessively long papers
will be rejected without review. 

Detailed formatting instructions and LaTeX/Word templates are available
at the workshop website, http://www.cs.virginia.edu/~skadron/tacs/

Organizers

Kevin Skadron, Univ. of Virginia Dept. of Computer Science 
Mircea Stan, Univ. of Virginia Dept. of Electrical and Computer
Engineering 

Program Committee

Sarita Adve, Univ. of Illinois at Urbana-Champaign 
Krste Asanovic, MIT 
Frank Bellosa, University of Erlangen-Nürnberg 
Pradip Bose, IBM TJ Watson 
David Brooks, Harvard 
José González, Intel Barcelona Research Center 
Steve Gunther, Intel 
Steve Kosonocky, IBM TJ Watson 
Avi Mendelson, Intel Israel 
Li-Shiuan Peh, Princeton 

Important Dates

Submission deadline:   April 5 
Author notification:   May 7 
Final manuscripts:     May 24

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* VPW2 Call for Papers

      Second Value-Prediction and Value-Based Optimization Workshop
                    http://www.csl.cornell.edu/VPW2/

                   to be held in conjunction with the

                  Eleventh International Conference on
   Architectural Support for Programming Languages and Operating Systems

                          Boston, Massachusetts
                          October 9 or 10, 2004

Theme
The Second Value-Prediction and Value-Based Optimization Workshop (VPW2) 
encompasses all hardware and software speculation mechanisms that make 
or use multi-bit predictions as well as value profiling and other 
value-based optimization techniques.

Topics
    - value predictors
    - confidence estimators
    - value profiling
    - value-based compiler optimizations
    - value-based power reduction
    - misprediction recovery schemes
    - latency predictors
    - dependency predictors
    - coherency predictors
    - address predictors (prefetchers)
    - branch predictors
    - etc.

Important Dates
Submission: July 29  (5pm EDT)
Notification: Sep. 2
Final paper: Sep. 23

Submission Guidelines
Submissions must use ten-point or larger fonts, one-inch margins, US 
letter size format, and are not to exceed six pages (including 
everything).  Submissions must be in PDF.  Please email submissions and 
questions to vpw2@csl.cornell.edu.

Organizers
Martin Burtscher (Cornell University)
Amer Diwan (University of Colorado at Boulder)

Program Committee
Lizy K. John (The University of Texas at Austin)
David R. Kaeli (Northeastern University)
Gabriel H. Loh (Intel / Georgia Institute of Technology)
Mary Lou Soffa (University of Pittsburgh)
Dean M. Tullsen (University of California, San Diego)
Benjamin G. Zorn (Microsoft)

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* SCOPES 2004 Call for Papers

				SCOPES 2004
		8th International Workshop on Software and
			Compilers for Embedded Systems
			September 2 - 3, 2004
		NH Amsterdam Centre hotel, Amsterdam
			http://www.scopes2004.org
**********************************************************************

The scope of the workshop is software for embedded systems. The
emphasis is on code generation techniques (compilers) for embedded
processors which consider their typical characteristics, for instance
heterogeneous register files, VLIW parallelism and special architectural
features for signal processing or microcontroller applications.

Topics of highest interest include:

- code generation for embedded processors
- compilers for reconfigurable architectures
- retargetable compilation techniques for fast design space exploration
- compilation for hardware/software co-design
- application specific programmable core/software development tools
co-design
- profiling and analysis techniques for embedded software
- optimizations for embedded Java
- specification and validation techniques for embedded software
- run-time support and real-time operating systems
- software synthesis
- exploitation of memory hierarchies
- optimization for low-power architectures
- design of embedded software

SCOPES 2004 solicits in particular papers on compilation and software
design for heterogeneous single chip multi-core processors, including
the partitioning and debugging of the software for such processors.

The plan is to have one day of the workshop devoted to compilers for
embedded processors and one day on general issues related to embedded
software and embedded processor architectures. In addition, there will
be a keynote presentation by a well-known speaker.

A key goal of the workshop is to provide an interactive atmosphere.
Questions are welcomed during all presentations. There will be sessions
to discuss specific topics. The workshop is open to all interested
participants active in the field.

Submitting Papers
Papers should present original, new research results not published
or submitted for publication in other forums. Papers should not exceed
15 pages (LNCS format) in postscript, PDF or RTF format. Papers should
be submitted using the submission page, which will be opened on
March 15th.

Important Dates
Abstracts due: April 8th, 2004. Strict paper submission deadline:
April 15th, 2004. Notification of acceptance: May 24th. The deadline
for the camera-ready final version is June 21st, 2004.

General chairs
- Marco Roodzant, ACE Associated Compiler Experts
- Henk Schepers, Philips Research

Local organisation
- Marianne Dalmolen, ACE Associated Compiler Experts

Program Committee
- Uwe Assmann, Linköpings Universitet
- Lex Augusteijn, Silicon Hive
- Shuvra Bhattacharyya, University of Maryland
- Albert Cohen, INRIA
- Alex Dean, North Carolina State University
- Nikil Dutt, University of California at Irvine
- Antonio González, Universitat Politècnica de Catalunya & Intel Labs
- David Gregg, Trinity College Dublin
- Rajiv Gupta, University of Arizona
- Seongsoo Hong, Seoul National University
- Nigel Horspool, Victoria University
- Masaharu Imai, Osaka University
- Ahmed Jerraya, IMAG
- Daniel Kästner, AbsInt
- Andreas Krall, Technische Universität Wien
- Rainer Leupers, RWTH Aachen
- Annie Liu, SUNY Stony Brook
- Peter Marwedel, Universität Dortmund
- Tatsuo Nakajima, Waseda University
- Alex Nicolau, University of California at Irvine
- Yunheung Paek, Seoul National University
- Santosh Pande, Georgia Institute of Technology
- Robert Pasko, IMEC
- Sreeranga Rajan, Fujitsu
- Miguel Santana, STMicroelectronics
- Hans van Someren, ACE Associated Compiler Experts
- Hiroyuki Tomiyama, Nagoya University
- Bernard Wess, Technische Universität Wien
- David Whalley, Florida State University

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* New papers published online by Computer Architecture Letters

Computer Architecture Letters announces our most recent paper, which is 
publicly available at
http://www.comp-arch-letters.org/2003paps.html.  We continue to seek new
submissions and remain committed to fast and accurate review.  Our mean
time to decision remains one month, with an acceptance rate of
approximately 21%.  For more information on submission, please see
http://www.comp-arch-letters.org

D. Citron. "Exploiting Low Entropy to Reduce Wire Delay." Volume 2, Jan. 
2004.

Abstract:

Wires shrink less efficiently than transistors. Smaller dimensions 
increase relative delay and the probability of crosstalk. Solutions to 
this problem include adding additional latency with pipelining, using 
``fat wires'' at higher metal levels, and advances in process and 
material technology.

We propose a stopgap solution to this problem by  applying a decade old 
technique called bus-expanding to the problem.  By exploiting low 
spatial and temporal entropy of data it is possible to transfer m bits 
of data over a n-bit wide bus in a single cycle (m > n). High entropy 
data will be routed directly over the bus while low entropy data will be 
compacted using small lookup tables. A table index will be transferred 
in the case of a successful lookup, otherwise the full value will be 
transferred in several cycles.

Reducing the number of wires per bus, enables the use of wider wires, 
which in turn reduces the wire delay. Examination of projected process 
technologies shows that by shrinking the number of bits in a bus (64 -> 
48) instead of shrinking the individual wires maintains a constant wire 
delay. Tests on SPEC CPU2000 have shown that for the 64-bit buses 
leading from the L1 caches to the processor core it is possible to 
transfer all data types (addresses, integers, instructions and 
floating-points) using 40-bits per bus on the average.

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