SIGARCH-MSG: February 2003 Digest of SIGARCH Messages

["Doug Burger" <dburger@cs.utexas.edu>]

This is the February 2003 Digest of SIGARCH Messages (sigarch-feb03):

* Obituary for Bob Rau
  http://www.hpl.hp.com/news/2003/jan_mar/rau.html
  Submitted by Norm Jouppi <Norm.Jouppi@hp.com>

* PACT'03 Call for Papers
  http://www.pactconf.org
  Submitted by David Kaeli <kaeli@ece.neu.edu>

* Hot Chips 15 Call for Contributions
  http://www.hotchips.org 
  Submitted by Alan Smith <smith@eecs.berkeley.edu>

* Latest papers in Computer Architecture Letters
  http://www.comp-arch-letters.org
  Submitted by Kevin Skadron <skadron@cs.virginia.edu>


--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@acm.org

* Archive: http://www.cs.wisc.edu/~lists/archive/sigarch-members/maillist.html
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  mail listserv@acm.org with message body: unsubscribe SIGARCH-MEMBERS

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Doug Burger			  Office:	       3.432 ACES
Assistant Professor		  Phone:	     512-471-9795
Department of Computer Sciences	  Assistant:	     512-471-9442
University of Texas at Austin     Fax:		     512-232-1413
Taylor Hall 2.124		  E-mail:   dburger@cs.utexas.edu
Austin, TX 78712-1188 USA	  www.cs.utexas.edu/users/dburger
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* Obituary for Bob Rau

As many of you have heard, Bob Rau, a pioneer in our field, passed
away recently.  His passing is a tremendous loss for our community.
His obituary can be found at the following location:

  http://www.hpl.hp.com/news/2003/jan_mar/rau.html

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* PACT'03 Call for Papers

                          PACT'03
            12th International Conference on
        Parallel Architectures and Compilation Techniques
             September 27 - October 1, 2003
         Chateau Sonesta Hotel, New Orleans, LA
                   http://www.pactconf.org
*****************************************************************

PACT-03 will be held in New Orleans, LA, a major cultural center of 
the southern United States.  The city offers such attractions as 
Mardi Gras, the French Quarter, Bourbon St., the Mississippi River 
and is the home of dixieland jazz.

PACT is a multi-disciplinary conference that brings together researchers 
from the hardware and software areas to present ground-breaking research 
related to parallel systems ranging across instruction-level parallelism, 
thread-level parallelism, multiprocessor parallelism and distributed systems.
PACT solicits papers on advances in architecture, compilers, languages and 
applications across a broad range of topics, including, but not limited to:

- Hardware/software optimizations for memory hierarchies
- Programming languages for parallel scientific and object-oriented applications
- Superscalar, VLIW, and multithreading architectures
- I/O, network processing and O/S issues for parallel computing
- Parallel aspects of power-aware and mobile/wireless computing
- Reconfigurable computing and novel parallel architectures
- Just-in-time/dynamic compilation for parallelism
- Parallel algorithms, computation models and simulation techniques
- Parallel software development tools supporting performance analysis/tuning 
  and debugging

Selected papers will be invited for publication in the 
Journal of Instruction Level Parallelism.  Please check 
the following web site for paper submission information:

		http://www.pactconf.org


***********************************************
Important Deadlines
Abstract Submission Deadline:	April 4,  2003
Full Paper Submission Deadline:	April 11, 2003
Author Notification:		June 20,  2003
Final Papers Due:		July 18,  2003 
***********************************************

General Chairs
David Kaeli, Northeastern University
David Koppelman, LSU  

Program Chairs
Mary Hall, USC/ISI
Vivek Sarkar, IBM 

Local Arrangements
J. Ramanujam, LSU

Finance Chair
Nikos Pitsianis, Duke University

Registration Chair
Diana Keen, Cal Poly

Tutorial Chair
Csaba Andras Moritz, U. of Massachusetts

Workshop Chair
Martin Schulz, Cornell University

Publications Chair
Bruce Childers, University of Pittsburgh

Publicity Chair
Dieter Kranzlmueller, Kepler University

Website Chair
Gene Cooperman, Northeastern University
Josep Llosa, UPC Barcelona

Travel Awards Chair
Lizy John, University of Texas, Austin

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* Hot Chips 15 Call for Contributions

                             HOT Chips 15 
                            
                         CALL FOR CONTRIBUTIONS 
                           Stanford University
                          Palo Alto, California 
                           August 17-19, 2003 

Since it began in 1989, Hot Chips has been known as one of the 
semiconductor industry's leading conferences on high-performance 
microprocessors and related integrated circuits. The conference is 
held once a year in August on the Stanford University campus in the 
center of the world's capital of electronics activity, Silicon Valley. 
The emphasis this year, as in previous years, is on real products and 
realizable technology. 

Topics of interest for this year's conference include but are
not limited to: 

*  Microprocessors 
*  Systems-on-chip 
*  Embedded processors 
*  Low-power chips 
*  Digital signal processors 
*  Performance evaluation 
*  Dynamic power management 
*  Application-specific processors 
*  Network/security processors 
*  Novel chips: quantum computing, microarray 
*  Graphics/Multimedia/Game processors 
*  Communication/networking chips 
*  Wireless LAN/Wireless WAN chips 
*  Reliability and design for test 
*  Compiler technology 
*  Operating system/chip interaction 
*  Reconfigurable processors 
*  Advanced semiconductor process technology 

Presentations at HOT Chips are in the form of 30-minute talks. 
Presentation slides will be published in the HOT Chips Proceedings. 
Participants are not required to submit written papers, but a select 
group will be invited to submit a paper for inclusion in a special 
issue of IEEE Micro. 

Submissions must consist of a title, extended abstract (three pages 
maximum), and the presenter's contact information (name, affiliation, 
job title, address, phone, fax, and email).  Please indicate whether 
you have submitted, intend to submit or have already presented or
published a similar or overlapping submission to another conference 
or journal.  Also indicate if you would like the submission to be 
held confidential; we do our best to maintain confidentiality.  

Submissions are evaluated by the Program Committee on the basis of the 
performance of the device (for devices), degree of innovation, use of 
advanced technology, potential market significance and anticipated
interest to the audience.  Research and software contributions will 
be evaluated with similar criteria.  Authors will be notified of the 
status of their submission by the end of April, 2003. 

Don't miss this chance to present your work to an audience of 
engineers, computer architects, and computer system and device
researchers.  Submissions must be received no later than March 15, 2003. 

Please make your submissions in plain ascii text (in the message, not
as an attachment) to:
        hotchips-submission@arith.stanford.edu 
(Submissions containing figures may be submitted in pdf, but plain
ascii is preferred.)

For more information, see the Hot Chips 15 Web site at: 
        http://www.hotchips.org 

Send questions to 
        hotchips@arith.stanford.edu             
or contact the co-program chairs:
Prof. Michael Flynn at  flynn@ee.stanford.edu, or
Pradeep K. Dubey at     pdubey@broadcom.com, 408-922-5904. 

Sponsored by the Technical Committee on Microprocessors and 
Microcomputers of the IEEE Computer Society 

See the HOT CHIPS 15 web page for updates: http://www.hotchips.org 

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* Latest papers in Computer Architecture Letters

Computer Architecture Letters is pleased to announce the publication of
two more papers online at our website,
<http://www.comp-arch-letters.org>; abstracts appear below.  The papers
will appear in print in our next paper issue.  The print issues are
distributed to the entire IEEE Computer Society TCCA membership, and
e-mail notifications of newly accepted papers are sent on a regular
basis to the TCCA and ACM SIGARCH memberships.

Papers:

- YC. Sohn, NH. Jung, SR. Maeng. "Request Reordering to Enhance the
Performance of Strict Consistency Models."

- K. A. Shaw, W. J. Dally. "Migration in Single Chip Multiprocessors."

The objective of Letters is to publish short (4-page), timely articles
of high-quality work.  We are very much aware of the long delays in our
field between submissions of manuscripts and their eventual appearance
in print.  We are doing something about that with this journal.  After
just over one year of operation, we have maintained an average
turnaround time from submission to author notification of just one
month, with an acceptance rate of 21%.

We encourage the community to continue submitting papers to Letters. 
Submissions are welcomed on any topic in computer architecture,
especially but not limited to: 
   - Microprocessor and multiprocessor systems 
   - Microarchitecture and ILP processors 
   - Workload characterization 
   - Performance evaluation and simulation techniques 
   - Compiler-hardware and operating system-hardware interactions 
   - Interconnect architectures 
   - Memory and cache systems 
   - Power and thermal issues at the architecture level 
   - I/O architectures and techniques 
   - Independent validation of previously published results 
   - Analysis of unsuccessful techniques 
   - Network and embedded-systems processors 
   - Real-time and high-availability architectures 
   - Reconfigurable systems 
The call for papers and instructions for submission can be found at
<http://www.comp-arch-letters.org>


Abstracts
---------

YC. Sohn, NH. Jung, SR. Maeng. "Request Reordering to Enhance the
Performance of Strict Consistency Models."

Abstract:
Advances in ILP techniques enable strict consistency 
models  to relax memory  order  through  speculative  execution  of 
memory  operations.    However,  ordering  constraints  still  hinder 
the  performance  because  speculatively  executed  operations 
cannot be committed out of program order for the possibility of 
mis-speculation. In this paper, we propose a new technique which 
allows memory operations to be non-speculatively committed out 
of order without violating consistency constraints.  


K. A. Shaw, W. J. Dally. "Migration in Single Chip Multiprocessors."

Abstract:
Global communication costs in future single-chip multiprocessors will
increase linearly with distance.  In this paper, we revisit the issues
of locality and load balance in order to take advantage of these new
costs.  We present a technique which simultaneously migrates data and
threads based on vectors specifying locality and resource usage.  This
technique improves performance on applications with distinguishable
locality and imbalanced resource usage.  64% of the ideal reduction
in execution time was achieved on an application with these traits
while no improvement was obtained on a balanced application with
little locality.

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