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SIGARCH-MSG: December 2002 Addendum to Digest of SIGARCH Messages
This is an addendum to the December 2002 Digest of SIGARCH Messages (sigarch-dec02a):
* HPCA-9 Call for Participation with Advance Program
http://www.cs.arizona.edu/hpca9
Submitted by Soner Onder <soner@mtu.edu>
* Terascale Performance Analysis Workshop
http://www-pablo.cs.uiuc.edu/Workshops/terascale.html
Submitted by Celso Mendes <cmendes@cs.uiuc.edu>
--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@acm.org
* Archive: http://www.cs.wisc.edu/~lists/archive/sigarch-members/maillist.html
* Web pages: http://www.cs.wisc.edu/~arch/www/, http://www.acm.org/sigarch/
* To remove yourself from the SIGARCH mailing list:
mail listserv@acm.org with message body: unsubscribe SIGARCH-MEMBERS
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Doug Burger Office: 3.432 ACES
Assistant Professor Phone: 512-471-9795
Department of Computer Sciences Assistant: 512-471-9442
University of Texas at Austin Fax: 512-232-1413
Taylor Hall 2.124 E-mail: dburger@cs.utexas.edu
Austin, TX 78712-1188 USA www.cs.utexas.edu/users/dburger
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* HPCA-9 Call for Participation with Advance Program
*--------------------------------------------------------------------*
* CALL FOR PARTICIPATION *
*--------------------------------------------------------------------*
HPCA - 9
Anaheim, California
February 8-12, 2003
The International Symposium on High-Performance Computer Architecture
provides a high quality forum for scientists and engineers to present
their latest research findings in this rapidly changing field. HPCA-9,
the ninth in the series of International Symposium on High Performance
Computer Architecture, will be held in Anaheim, California.
Please visit the conference web page at:
http://www.cs.arizona.edu/hpca9
ON-LINE REGISTRATION is now OPEN.
EARLY REGISTRATION DEADLINE: 5:00pm Eastern FRIDAY, JANUARY 17, 2003.
*****============================================================*****
* ADVANCE PROGRAM *
*****============================================================*****
*====================================================================*
* Saturday, February 8 *
*====================================================================*
Workshops (8:00am - 5:00pm)
---------------------------
INTERACT-7
The 7th Annual Workshop on Interaction between Compilers and
Computer Architecture
SAN-2
2nd Annual Workshop on Novel Uses of System Area Networks
Tutorial (Afternoon)
--------------------
An introduction to Network Processors
Patrick Crowley, U. Washington
*====================================================================*
* Sunday, February 9 *
*====================================================================*
Workshops (8:00am - 5:00pm)
---------------------------
CAECW
Sixth Workshop on Computer Architecture
Evaluation using Commercial Workloads
NP-2
The Second Workshop on Network Processors
SSRS
Workshop on Software Support for Reconfigurable
Systems
Tutorial (Morning)
--------------------
New Computing Platforms for Embedded Systems
Frank Vahid & Walid Najjar, U. California Riverside
Tutorial (Afternoon)
--------------------
Simics Microarchitect's Toolset
Peter Magnuson, Virtutech
*====================================================================*
* Monday, February 10 *
*====================================================================*
----------------------------------------------------------------------
Welcome (8:45am - 9:00am)
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----------------------------------------------------------------------
Keynote I (9:00am - 10:00am)
----------------------------------------------------------------------
Billion Transistor Chips in Mainstream Enterprise Platforms of
the Future
Dileep Bhandarkar
Architect-at-large, Enterprise Platforms Group, Intel Corporation
----------------------------------------------------------------------
----------------------------------------------------------------------
Break (10:00 am - 10:30 am)
----------------------------------------------------------------------
----------------------------------------------------------------------
Session 1 : Multithreading (10:30am -- 12:00n)
Variability in Architectural Simulations of Multi-threaded
Workloads
Alaa Alameldeen and David Wood
Mini-threads: Increasing TLP on Small-Scale SMT Processors
Joshua Redstone, Susan Eggers, and Henry Levy
Front-End Policies for Improved Issue Efficiency in SMT
Processors
Ali El-Moursy and David Albonesi
----------------------------------------------------------------------
----------------------------------------------------------------------
Lunch (12:00n - 1:30pm)
----------------------------------------------------------------------
----------------------------------------------------------------------
Session 2 : Branch Prediction (1:30pm - 3:00pm)
Reconsidering Complex Branch Predictors
Daniel Jimenez
Incorporating Predicate Information Into Branch Predictors
Beth Simon, Brad Calder, and Jeanne Ferrante
Dynamic Data Dependence Tracking and its Application to Branch
Prediction
Lei Chen, Steve Dropsho, and David Albonesi
----------------------------------------------------------------------
----------------------------------------------------------------------
Break (3:00pm - 3:30 pm)
----------------------------------------------------------------------
----------------------------------------------------------------------
Session 3 : Power Efficient Designs (3:30pm - 5:30pm)
Control Techniques to Eliminate Voltage Emergencies in
High-Performance Processors
Russ Joseph, David Brooks, and Margaret Martonosi
Dynamic Voltage Scaling with Links for Power Optimization of
Interconnection Networks
Li Shang, Li-Shiuan Peh, and Niraj Jha
Power-Aware Control Speculation through Selective Throttling
Juan L. Aragon, Jose Gonzalez, and Antonio Gonzalez
Deterministic Clock Gating For Microprocessor Power Reduction
Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, and
T.N. Vijaykumar
----------------------------------------------------------------------
----------------------------------------------------------------------
BANQUET
----------------------------------------------------------------------
*====================================================================*
* Tuesday, February 11 *
*====================================================================*
----------------------------------------------------------------------
Keynote II (8:30am - 9:30am)
Beyond Performance: Some (other) Challenges for Future
Microprocessors.
Eric Kronstadt
Director, VLSI Systems, IBM TJ Watson
----------------------------------------------------------------------
----------------------------------------------------------------------
Break (9:30am - 10:00am)
----------------------------------------------------------------------
----------------------------------------------------------------------
Session 4 : Superscalars (10:00am - 12:00n)
Runahead Execution: An Alternative to Very Large Instruction
Windows for Out-of-order Processors
Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale Patt
Microarchitecture and Performance Analysis of a SPARC-V9
Microprocessor for Enterprise Server Systems
Mariko Sakamoto, Akira Katsuno, Alichiro Inoue, Takeo Asakawa,
Haruhiko Ueno, and Kuniki Morita
Exploring the VLSI Scalability of Stream Processors
Brucek Khailany, William J. Dally, Scott Rixner, Ujval J. Kapasi,
John Owens, and Brain Towles
Dynamic Optimization Of Micro-Operations
Brian Slechta, Brian Fahs, David Crowe, Michael Fertig,
Gregory Muthler, Justin Quek Francesco Spadini,
Sanjay J. Patel, and Steven S. Lumetta
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----------------------------------------------------------------------
Luncheon (12:00n - 1:30pm)
----------------------------------------------------------------------
----------------------------------------------------------------------
Session 5 : Multiprocessor Systems (1:30pm - 3:00pm)
Slipstream Execution Mode for CMP-Based Multiprocessors
Khaled Ibrahim, Gregory Byrd, and Eric Rotenberg
Tradeoffs in Buffering Memory State for Thread-Level Speculation
in Multiprocessors
Maria Garzaran, Milos Prvulovic, Victor Vinals, Jose Llaberia,
Lawrence Rauchwerger, and Josep Torrellas
Dynamic Data Replication: An approach to Providing Fault-Tolerant
Shared Memory Clusters
Rosalia Christodoulopoulou, Reza Azimi, and Angelos Bilas
----------------------------------------------------------------------
----------------------------------------------------------------------
Break (3:00pm - 3:30pm)
----------------------------------------------------------------------
----------------------------------------------------------------------
Session 6 : Memory and Communication Performance (3:30pm - 5:30pm)
Memory System Behavior of Java-Based Middleware
Martin Karlsson, Kevin Moore, Erik Hagersten, and David Wood
Evaluating the Impact of Communication Architecture on the
Performability of Cluster-Based Services
Kiran Nagaraja, Neeraj Krishnan, Ricardo Bianchini,
Richard Martin, and Thu Nguyen
Hierarchical Back-Off Lock for Non-Uniform Communication
Architectures
Zoran Radovic and Erik Hagersten
Performance Enhancement Techniques for InfiniBand Architecture
Eun Jung Kim, Ki Hwan Yum, Chita Das, Mazin Yousif,
and Jose Duato
----------------------------------------------------------------------
*====================================================================*
* Wednesday, February 12 *
*====================================================================*
----------------------------------------------------------------------
Keynote III (8:00am - 9:00am)
The State of State
Peter Kogge
McCourtney Professor of Computer Science and Engineering,
University of Notre Dame
----------------------------------------------------------------------
----------------------------------------------------------------------
Session 7 : Profiling and Simulation Support (9:00am - 10:00am)
Catching Accurate Profiles in Hardware
Satish Narayanasamy, Timothy Sherwood, Suleyman Sair,
Brad Calder, and George Varghese
A Statistically Rigorous Approach for Improving Simulation
Methodology
Joshua Yi, David Lilja, and Douglas Hawkins
----------------------------------------------------------------------
----------------------------------------------------------------------
Break (10:00am - 10:30am)
----------------------------------------------------------------------
----------------------------------------------------------------------
Session 8 (10:30 am - 12:30 pm)
8A - Caching and Prefetching
----------------------------
Caches and Merkle Trees for Efficient Memory Authentication
Blaise Gassend, Ed Suh, Dwaine Clarke, Marten van Dijk,
and Srinivas Devadas
Just Say No: Benefits of Early Cache Miss Determination
Gokhan Memik, Glenn Reinman, and William Mangione-Smith
TCP: Tag Correlating Prefetchers
Zhigang Hu, Stefanos Kaxiras, and Margaret Martonosi
Cost-sensitive Cache Replacement Algorithms
Jaeheon Jeong and Michel Dubois
8B - Networks and Communication
-------------------------------
Scalar Operand Networks
Michael Taylor, Walter Lee, Saman Amarasinghe, and
Anant Agarwal
Inter-cluster Communication Models for Clustered VLIW processors
Andrei Terechko, Erwan Le Thenaff, Manish Garg,
Jos van Eijndhoven, and Henk Corporaal
A Methodology for Designing Efficient On-Chip Interconnects
on Well-behaved Communication Patterns
Wai Hong Ho and Timothy Pinkston
Active I/O Switches in System Area Networks
Ming Hao and Mark Heinrich
----------------------------------------------------------------------
----------------------------------------------------------------------
========================================================================
* Terascale Performance Analysis Workshop
June 2 - 4 , 2003
Melbourne - Australia
In conjunction with ICCS'2003 - International Conference on Computational
Science
------------------------------------------------------------------------
Scope
Terascale systems, composed of hundreds or thousands of processors, complex
interconnection networks, and large numbers of storage devices, pose
daunting problems for performance instrumentation, analysis, and
optimization. This workshop will explore approaches to application and
system measurement, performance diagnosis, and model construction. Those
approaches include tools or methodologies that advance the current state of
the art on how to achieve significant performance levels for scientific
applications on current terascale and future petascale systems. Hardware
performance measurements, instrumented libraries, and schemes for automatic
adaptation to changing system behavior will also be explored.
------------------------------------------------------------------------
Workshop Organizers
Dan Reed (National Center for Supercomputing Applications)
Celso Mendes (University of Illinois, Dep. Computer Science)
Radha Nandkumar (National Center for Supercomputing Applications)
Rob Pennington (National Center for Supercomputing Applications)
John Towns (National Center for Supercomputing Applications)
------------------------------------------------------------------------
Call for Papers
Topics of interest for this workshop include, but are not limited to, the
following:
* Application performance measurement
* Case studies in scaling applications to 1000+ processors
* Measurement techniques applicable to large systems
* Performance diagnosis and code tuning
* Scalable performance models
* Techniques to achieve scaling in real applications
* Tools for efficient performance assessment
* Use of hardware performance counters
* Performance data reduction techniques
* Instrumented libraries and utilities
* Performance extrapolation and prediction
* Automatic performance adaptation
* Fault tolerance and checkpoint/restart strategies
Submissions are invited for work in these areas not published previously.
Every submission will be peer-reviewed. Submissions should be in PDF or
Postscript formats, and should not exceed ten printed pages in length,
including all sections. All submissions should be sent by e-mail to
cmendes@cs.uiuc.edu in a note under the subject "iccs03-terascale"; in this
note, please specify also the name/e-mail of the major contact author and of
the presenting author.
Accepted submissions will be presented at the workshop and will be
published, with other ICCS'2003 papers, in a special edition of Springer
Verlag's Lecture Notes in Computer Science (LNCS). The final version of
accepted papers should conform to the LNCS guidelines.
------------------------------------------------------------------------
Important Dates
* Paper submission deadline: January 10, 2003 (No extensions)
* Author notification: January 31, 2003
* Final paper due: February 14, 2003
------------------------------------------------------------------------
Contact Information
Daniel A. Reed
E-mail: reed@ncsa.uiuc.edu
National Center for Supercomputing Applications
605 East Springfield Avenue
Champaign, IL 61820 - USA
Phone (217) 244-0078
Celso L. Mendes
E-mail: cmendes@cs.uiuc.edu
University of Illinois - Department of Computer Science
1304 West Springfield Avenue
Urbana, IL 61801 - USA
Phone (217) 244-9234
------------------------------------------------------------------------
Workshop URL: http://www-pablo.cs.uiuc.edu/Workshops/terascale.html
ICCS'2003 URL: http://www.science.uva.nl/events/ICCS2003
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