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SIGARCH-MSG: October 2002 Digest of SIGARCH Messages
This is the October 2002 Digest of SIGARCH Messages (sigarch-oct02):
* ISCA 2003 Call for Papers
http://isca03.cs.princeton.edu/
Submitted by Kai Li <li@cs.princeton.edu>
* SIGMETRICS 2003 Call for Papers
http://www.crhc.uiuc.edu/sigm2003
Submitted by Dan Rubenstein <danr@cs.columbia.edu>
* Workshop on Network Processors Call for Papers
http://www.cs.washington.edu/NP2
Submitted by Patrick Crowley <pcrowley@cs.washington.edu>
* New papers published by Computer Architecture Letters
http://www.cs.virginia.edu/~tcca/ca_letters_cfp.html
Submitted by Kevin Skadron <skadron@cs.virginia.edu>
--Doug Burger
SIGARCH Information Director
infodir_SIGARCH@acm.org
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Doug Burger Office: 3.432 ACES
Assistant Professor Phone: 512-471-9795
Department of Computer Sciences Assistant: 512-471-9442
University of Texas at Austin Fax: 512-232-1413
Taylor Hall 2.124 E-mail: dburger@cs.utexas.edu
Austin, TX 78712-1188 USA www.cs.utexas.edu/users/dburger
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* ISCA 2003 Call for Papers
Call for Papers
The 30th Annual International Symposium on Computer Architecture
ISCA 2003
ISCA has been a premier forum to present and discuss innovative ideas
and quantified experience in the area of computer architecture.
Architecture today is quite different from it has been in the past.
Thus, the 30th ISCA looks to focus on architecture in the broad sense,
looking at architectures for specific application areas, and system
architecture issues. While more conventional architecture papers will
be considered, innovative architectures that address a specific
application domain, or novel approaches to solve the problems of
computing systems will be encouraged. Topics include but not limited
to:
* computer system architectures,
* processor architectures,
* power-efficient architectures,
* multiprocessors and multicomputers,
* memory hierarchy subsystems,
* storage subsystem architectures,
* network processor and router architectures,
* application-specific, or embedded architectures,
* architectures for secure computing,
* architectural implications and application characteristics, and
* performance evaluation and measurement of real systems.
We particularly encourage submissions containing highly original
ideas.
The submission process for ISCA 2003 will include two parts: an
abstract and a paper submission. The abstract includes a description
(100-300 words) of the paper and an indication of the key topics of
the paper. The ABSTACT DEADLINE for submissions is NOVEMBER 11, 2002
at 6PM PST (US). The PAPER DEADLINE for submissions is one week later,
NOVEMBER 18, 2002 at 6PM PST (US). NO FURTHER EXTENSIONS WILL BE
GRANTED. Authors are required to submit both the abstract and paper
electronically at: http://isca03.cs.princeton.edu/
Your paper should be formatted in PDF format for letter-size paper.
Submissions must be viewable by Adobe Acrobat Reader (version 3.0 or
higher). The submission should not exceed 7000 words or 10 pages of
conference paper format using 10pt fonts. Submissions exceeding the
required limit will not be reviewed by the program committee.
Finally, it is requested that authors should not disclose their
identity, as they will be reviewed blind. Submissions will be judged
on originality, significance, interest, clarity, and correctness.
ISCA requires that papers not be submitted simultaneously to any other
conferences or publications, that submissions not be previously
published, and that accepted papers not be subsequently published
elsewhere.
All submissions will be acknowledged by November 25, 2002. If your
submission is not acknowledged by this date, please contact the
program chairs promptly at isca03pcchair@cs.princeton.edu.
Program Committee
David August, Princeton University
Krste Asanovic, MIT
Todd Austin, University of Michigan
Alan Berenbaum, Independent Consultant
Angelos Bilas, University of Toronto
Andrew A. Chien, University of California at San Deigo
Sandhya Dwarkadas, University of Rochester
Joel Emer, Intel
Babak Falsafi, Carnegie Mellon University
Josh Fisher, HP Labs
Antonio Gonzalez, Universitat Polithcnica de Catalunya and Intel Labs
James Goodman, University of Wisconsin at Madison
Dirk Grunwald, University of Colorado
Mark Horowitz, Stanford University
Wen-mei Hwu, University of Illinois at Urbana-Champaign
Liviu Iftode, University of Maryland at College Park
Mary Jane Irwin, Penn State University
Norman Jouppi, HP Labs
Stephen W. Keckler, University of Texas at Austin
Dan Lenoski, CISCO
Rich Oehler, Newisys
David Patterson, University of California at Berkeley
Steve Scott, Cray
John Shen, Intel
Jim Smith, University of Wisconsin at Madison
T. Basil Smith, IBM Watson
Per Stenstrom, Chalmers University of Technology
Chuck Thacker, Microsoft
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* SIGMETRICS 2003 Call for Papers
Call for Papers
****** ACM SIGMETRICS 2003 ******
International Conference on
Measurement and Modeling of Computer Systems
June 10-14, 2003
San Diego, California
http://www.crhc.uiuc.edu/sigm2003
(held in conjunction with FCRC'03 (http://www.acm.org/fcrc)
The SIGMETRICS conference solicits papers on the development and
application of state-of-the-art, broadly applicable analytic,
simulation, and measurement-based performance evaluation techniques.
We are interested in techniques whose aim is to evaluate a system's
dependability, security, correctness, or power consumption as well as
more traditional performance metrics. Of particular interest is work
that furthers the state of the art in performance evaluation methods,
or that creatively applies previously developed methods to gain
important insights into key design trade-offs in complex computer and
communication systems.
Topics of interest include but are not limited to:
- Performance-oriented design and evaluation studies of communication
networks, Internet servers, computer architectures, database
systems, operating systems, distributed systems, multimedia systems,
mobile and handheld systems, file and I/O systems, memory systems,
real-time systems, and dependable systems, including case studies
and performance-evaluation tools.
- Performance methodology techniques, algorithms, and tools for
analytic modeling, system measurement and monitoring, model
verification and validation, workload characterization, simulation,
statistical analysis, stochastic modeling including queues,
stochastic Petri nets, stochastic process algebras, experimental
design, reliability and availability analysis, power analysis,
performance optimizations, and hybrid models.
Submission Guidelines
=====================
- Papers: On October 25, 2002, authors must submit the title,
abstract, and author list (with affiliations) for their intended
submission. Submissions of the full papers are due on November 1,
2002 and should not exceed 20 double-spaced pages, including figures
and tables. Papers must be submitted electronically in printable
postscript or PDF form. All submissions will be reviewed using a
double-blind review process. The identity of the authors and
referees will not be revealed to each other. To ensure blind
reviewing, authors' names and affiliations MUST NOT appear in the
paper; bibliographic references must be made in such as way as to
preserve author anonymity. See the web site for more information on
submission.
- Hot Topic Sessions: Proposals are solicited for a hot topic session,
in which a group of speakers will present and discuss their recent
results in an area. Send proposals to the program chairs,
identifying the organizer of the session, the session title, three
to five speakers, the titles of their talks, and a short abstract of
each talk.
- Tutorials: A series of tutorials will immediately precede the main
conference. Send proposals of no more than 1 or 2 pages (for
90-minute or 3-hour tutorials) to the tutorials chair. Include the
proposed title, brief description of material, intended audience,
assumed background of attendees, and the name, affiliation, contact
information (e-mail and phone), and brief biography of speaker(s).
Postscript or PDF is preferred.
Important Dates:
================
Title, abstract, and author affiliations due by: October 25, 2002
Paper, tutorial, and hot topic proposal
submission deadline: November 1, 2002
(HARD deadline)
Notification of acceptance: January 24, 2003
Organization
============
General Co-Chairs:
Satish Tripathi (UC Riverside) tripathi@engr.ucr.edu
Bill Cheng (TeleGIF) bill.cheng@telegif.org
Program Co-Chairs:
Jennifer Rexford (AT&T Labs-Research) jrex@research.att.com
William H. Sanders (U Illinois) whs@crhc.uiuc.edu
Tutorial Co-Chairs:
Steven Low (Caltech) slow@caltech.edu
John C.S. Lui (Chinese U. Hong Kong) cslui@cse.cuhk.edu.hk
Proceedings Chair:
Evgenia Smirni (College of William & Mary) esmirni@cs.wm.edu
Publicity Chair:
Dan Rubenstein (Columbia U.) danr@ee.columbia.edu
Technical Program Committee:
Vikram Adve (U Illinois)
Marco Ajmone-Marsan (Politecnico di Torino)
Gianfranco Balbo (U degli Studi di Torino)
Paul Barford (U Wisconsin-Madison)
Ernst Biersack (Institut Eurecom)
Gianfranco Ciardo (College of William & Mary)
E. G. Coffman, Jr. (Columbia U)
Edmundo de Souza e Silva (UFRJ)
Derek Eager (U Saskatchewan)
E. N. Elnozahy (IBM Research, Austin)
Lixin Gao (UMass-Amherst)
Ashish Goel (USC)
Leana Golubchik (USC)
Ramesh Govindan (ICSI and USC)
Mor Harchol-Balter (Carnegie Mellon)
Richard E. Harper (IBM Research)
Boudewijn R. Haverkort (RWTH-Aachen)
Kimberly Keeton (HP Labs)
Marwan M. Krunz (U Arizona)
Srisankar Kunniyur (U Pennsylvania)
Jim Kurose (UMass-Amherst)
Zhen Liu (IBM Research)
Robert Morris (MIT)
Richard R. Muntz (UCLA)
Philippe Nain (INRIA)
Venkata N. Padmanabhan (Microsoft Research)
Vivek Pai (Princeton)
Gerardo Rubino (IRISA/INRIA)
Srinivasan Seshan (Carnegie Mellon)
Ken Sevcik (U Toronto)
Evgenia Smirni (College of William & Mary)
Nina Taft (Sprint ATL)
Nitin Vaidya (U Illinois)
Mary K. Vernon (U Wisconsin-Madison)
C. Murray Woodside (Carleton U.)
Ellen W. Zegura (Georgia Tech)
Zhi-Li Zhang (U Minnesota)
For more and up to date information see the conference web site
at: http://www.crhc.uiuc.edu/sigm2003
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*********************************************************************
CALL FOR PAPERS
*********************************************************************
Workshop on Network Processors
http://www.cs.washington.edu/NP2/
Anaheim, California
February 9, 2003
Held in conjunction with HPCA 9 - The 9th International
Symposium on High-Performance Computer Architecture
http://www.cs.arizona.edu/hpca9/
February 8-12, 2003
OVERVIEW
As the performance and importance of digital communication networks
have increased, so have the challenges in network component design. To
meet ever-escalating performance, flexibility and economy
requirements, the networking industry has opted to build products
around network processors. These processors are programmable yet
application-specific; their designs are tailored to efficiently
implement communications applications such as: routing, protocol
analysis, voice and data convergence, firewalls, VPNs, and QoS. The
term network processor is used here in the most generic sense -- from
task-specific processors, such as classification and encryption
engines, to more general-purpose packet or communications processors.
Network processor design is an emerging field with numerous challenges
and opportunities. The goal of this workshop is to provide a forum for
engineers and scientists from academia and industry to discuss their
latest research in the architecture, design, programming, and use of
these devices. We are especially interested in attracting new or
experimental techniques and approaches.
IMPORTANT DATES
Papers due : November 1, 2002
Notification to authors : January 6, 2003
Final papers due: January 24, 2003
TOPICS
Topics of particular interest include, but are not limited to:
* Architectures for network, communications, or packet processors
* Network Processor theory of design
* Novel commercial product designs
* Search engines
* Benchmarking and performance analysis
* Coprocessors such as CAMs and other support devices
* Interfaces to high-speed packet buses and switch fabrics
* Techniques for accelerating network services
* Voice processing and packet telephony
* Software aspects of programming processors for networking
* Applications, including packet forwarding, packet classification,
QoS, encryption and security, compression, etc.
The workshop will consist of a keynote address, paper presentations
and a panel session. In addition to academic and research
contributions, product descriptions that focus on architecture
(hardware or software) or performance analysis will also be
considered. Attendees will receive a copy of workshop papers. After
the workshop, selected papers will be published in a book entitled
Network Processor Design: Issues and Practices Volume II (Morgan
Kaufman Publishers).
SUBMISSIONS
Please submit full papers (single spaced, font size 11, 1 inch
margins, not exceeding 15 pages) in Adobe PDF format for review to
pcrowley@cs.washington.edu.
PROGRAM COMMITTEE
Anant Agarwal, MIT
Andrew Campbell, Columbia University
Patrick Crowley, University of Washington
Mark Franklin, Washington University in St. Louis
Haldun Hadimioglu, Polytechnic University
Kenneth Mackenzie, Georgia Tech
Bill Mangione-Smith, UCLA
John Marshall, Cisco Systems
Danial Mylnek, EPFL (Switzerland)
Mohammad Peyravian, IBM Corporation
Dimitrios Stiliadis, Bell Labs
Jonathan Turner, Washington University in St. Louis
Mateo Valero, UPC (Spain)
Tilman Wolf, University of Massachusetts
Peter Z. Onufryk, IDT
Raj Yavatkar, Intel Corporation
ORGANIZERS
Patrick Crowley, University of Washington (pcrowley@cs.washington.edu)
Mark Franklin, Washington University in St. Louis (jbf@ccrc.wustl.edu)
Haldun Hadimioglu, Polytechnic University (haldun@photon.poly.edu)
Peter Z. Onufryk, IDT (peter.onufryk@idt.com)
NOTES FROM NP1 (2002):
Selected papers from NP1 and additional industry contributions will
appear in Network Processor Design : Issues and Practices Volume I
(Morgan Kaufmann Publishers, September 2002).
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* New papers published by Computer Architecture Letters
To provide the fastest possible online publication, Computer
Architecture Letters continues to announce newly accepted papers in
this monthly e-mail to the SIGARCH and TCCA memberships. These papers
can be obtained from our website, http://comp-arch-letters.org
- S. Tambat, S. Vajapeyam. "Page-Level Behavior of Cache Contention."
Volume 1, Jul. 2002.
- P. Juang, P. Diodato, S. Kaxiras, K. Skadron, Z. Hu, M. Martonosi,
D. W. Clark. "Implementing Decay Techniques using 4T Quasi-Static
Memory Cells." Volume 1, Sep. 2002.
"Letters" is a quarterly forum for fast publication of new,
high-quality ideas in the form of short, critically refereed,
technical papers. Accepted letters are published immediately on our
website and in the next available paper issue. Submissions are
accepted on a continuing basis. Current turn-around time is 33 days,
and we hope to improve this as our review process becomes more
efficient. Current acceptance rate is 20%. The kind of paper that we
are seeking is an early, "wow" idea that may not yet be ready for a
full conference publication, but has enough validated insights to
justify publication as a four-page letter.
Abstracts
---------
- S. Tambat, S. Vajapeyam. "Page-Level Behavior of Cache Contention."
Volume 1, Jul. 2002.
Cache misses in small, limited -associativity primary caches
very often replace live cache blocks, given the dominance of capacity
and conflict misses. Towards motivating novel cache organizations, we
study the comparative characteristics of the virtual memory address
pairs involved in typical primary -cache contention (block
replacements) for the SPEC2000 integer benchmarks. We focus on the
cache tag bits, and results show that (i) often just a few tag bits
differ between contending addresses, and (ii) accesses to certain
segments or page groups of the virtual address space (i.e. certain
tag-bit groups) contend frequently. Cacheconscious virtual address
space allocation can further reduce the number of confl icting tag
bits. We mention two directions for exploiting such page -level
contention patterns to improve cache cost and performance.
- P. Juang, P. Diodato, S. Kaxiras, K. Skadron, Z. Hu, M. Martonosi,
D. W. Clark. "Implementing Decay Techniques using 4T Quasi-Static
Memory Cells." Volume 1, Sep. 2002.
This paper proposes the use of four-transistor (4T) cache and
branch predictor array cell designs to address increasing worries
regarding leakage power dissipation. While 4T designs lose state when
infrequently accessed, they have very low leakage, smaller area, and
no capacitive loads to switch. This short paper gives an overview of
4T implementation issues and a preliminary evaluation of
leakage-energy savings that shows improvements of 60-80\%.
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