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SIGARCH-MSG: November 2000 Digest of SIGARCH Messsages
Attached is the SIGARCH mailing list digest for November
(grep sigarch-nov00):
* SIGARCH Conference (Program Committee) Guidelines posted at URL
http://www.acm.org/sigarch/conference_guidelines.html
* CFP for ASPLOS-IX Conference and Workshops
* CFP for Workshop on Parallel and Distributed Scientific and Engineering
Computing with Applications (PDSECA-01)
* Kool Chips Workshop at MICRO33
* Removing yourself from SIGARCH mailing list
--Mark Hill
infodir_SIGARCH@acm.org
SIARCH Information Director
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Mark D. Hill Office 6373 CSS
Professor & Romnes Fellow Phone 608-262-2196
Computer Sciences Department Asstnt 608-265-3402
University of Wisconsin-Madison FAX 608-262-9777
1210 West Dayton Street E-mail markhill@cs.wisc.edu
Madison, WI 53706-1685 USA http://www.cs.wisc.edu/~markhill
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SIGARCH Conference Guidelines Posted
I have put the SIGARCH Conference Guidelines off the SIGARCH web page
at URL:
http://www.acm.org/sigarch/conference_guidelines.html
These are guidelines to program committees of SIGARCH sponsored
conferences. They were authored by David Patterson and adopted on
April 20, 1994.
--Mark Hill
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ASPLOS-IX Conference and Workshops CFP
Enclosed is the call for participation for the 2nd Workshop on
Intelligent Memory Systems which will be held in conjection with the
ASPLOS-IX conference, and a reminder that early registration for the
ASPLOS-IX conference and workshops ends Oct 20, 2000.
ASPLOS-IX, sponsosred by ACM SIGARCH, SIGOPS and SIGPLAN, is a
multi-disciplinary conference, cross-fertilizing research in areas of
hardware, architecture, compilers, operating systems, networking, and
applications. It will be held Nov 12-15, 2000 in Cambridge, MA, with
workshops and tutorials on Nov 12, and the conference proper from Nov
13-15. For further details including an advance program and
registration information, please see:
http://foothill.lcs.mit.edu/asplos-ix
Early registration for the conference and workshops ends Oct 20, 2000.
Pre-registration ends Nov 3, 2000. The conference hotel, Royal
Sonesta Hotel, has agreed to hold a limited number of rooms for
conference attendees until Oct 18, 2000.
Please accept our apology if you receive multiple copies of this
message.
Sincerely,
Boon S Ang
Publicity Chair
ASPLOS-IX Conference
Call for Participation
The 2nd Workshop on Intelligent Memory Systems
November 12, 2000
Boston, Massachusetts
In conjunction with ASPLOS-IX
http://arch.cs.ucdavis.edu/ims00
Increasing chip densities and inter-chip communication costs
continue to fuel interest in intelligent memory systems.
Since the First Workshop on Mixing Logic and DRAM in 1997,
technologies and systems for computation in memory have
developed quickly. The focus of this workshop is to bring
together researchers from academia and industry to discuss
recent progress and future goals.
Please register at the ASPLOS IX homepage:
http://foothill.lcs.mit.edu/asplos-ix
Preliminary workshop schedule
08:30 Opening Remarks
08:40 Session 1: Memory Technology
Invited Talk: Embedded DRAM--Technology and Challenges
Subu Iyer
IBM Microelectronics
A 64Mbit Mesochronous Hybrid Wave Pipelined Multi-bank DRAM
Macro
Junju Ogawa and Mark Horowitz
Fujitsu Laboratories of America and Stanford University
Software Controlled Reconfigurable On-Chip Memory for High
Performance Computing
Hiroshi Nakamura, Masaki Kondo and Taisuke Boku
University of Tokyo and University of Tsukuba
10:15 Break
10:45 Session 2: Architecture
Content-based Prefetching: Initial Results
Robert Cooksey, Dennis Colarelli, and Dirk Grunwald
University of Colorado
Memory System Support for Dynamic Cacheline Assembly
Lixin Zhang, Venkata K. Pingali, Bharat Chandramouli,
and John B. Carter
Unversity of Utah
Adaptively Mapping Code in an Intelligent Memory
Architecture
Yan Solihin, Jaejin Lee and Josep Torrellas
University of Illinois at Urbana-Champaign and
Michigan State University
12:00 Lunch
13:00 Poster session
14:00 Session 3: Applications and Operating Systems
Invited Talk: IBM Blue Gene
Mark Snir
IBM T.J. Watson Research Center
The Characterization of Date Intensive Memory Workloads on
Distributed PIM Architectures
Richard C. Murphy, Peter M. Kogge and Arun Rodrigues
University of Notre Dame
Memory Management in a PIM-Based Architecture
Mary Hall and Craig Steele
USC Information Sciences Institute
15:35 Break
16:00 Session 4: Compilers
Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler
David Judd and Katherine Yelick
University of California, Berkeley
FlexCache: A Framework for Flexible Compiler Generated Data
Caching
Csaba Andras Moritz, Matthew Frank and Saman Amarasinghe
MIT
16:50 Open-mike session
17:20 Closing Remarks
Workshop Chairs:
Fred Chong (UC Davis) and Christoforos Kozyrakis (UC Berkeley)
Steering Committee:
David Patterson (UC Berkeley) and Mark Horowitz (Stanford)
Publicity and Publications:
Mark Oskin (UC Davis)
Program Committee:
- Krste Asanovic (MIT)
- John Carter (Utah)
- Fred Chong (UC Davis)
- Nikkil Dutt (UC Irvine)
- Jose Fortes (Purdue)
- John Granacki (USC)
- Patrick Hanrahan (Stanford)
- Peter Kogge (Notre Dame)
- Christoforos Kozyrakis (UC Berkeley)
- Konrad Lai (Intel)
- Kazuaki Murakami (Kyushu U.)
- Josep Torrellas (UIUC)
- Woodward Yang (Harvard)
Submitted by: "Ang, Boon" <boonang@exch.hpl.hp.com>
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CALL FOR PAPERS
The 2nd Workshop on Parallel and Distributed Scientific and Engineering
Computing with Applications (PDSECA-01)
http://www.stfx.ca/people/lyang/activities/ipdps01-pdseca.html
Hyatt Regency San Francisco Airport, San Francisco
April 23-27, 2001
in conjunction with
The 15th International Parallel and Distributed Processing Symposium
(IPDPS-2001)
http://www.ipdps.org/ipdps2001
Scope and Interests:
Parallel and distributed scientific and engineering computing has become a
key technology which will play an important part in determining, or at least
shaping, future research and development activities in many academic and
industrial branches. This special workshop is to bring together computer
scientists, applied mathematicians and researchers to present, discuss and
exchange idea, results, work in progress and experience of research in the
area of parallel and distributed computing for problems in science and
engineering applications.
Among the main topics (but not limited to) are:
* development of advanced parallel and distributed methods
* parallel and distributed computing techniques and codes,
* practical experiences using various supercomputers with software
such as MPI, PVM, and High Performance Fortran, OpenMP, etc.
* applications to the following areas:
* computational fluid dynamics and mechanics
* material sciences
* space, weather, climate systems and global changes
* computational environment and energy systems
* computational ocean and earth sciences
* combustion system simulation
* computational chemistry
* computational physics
* bioinformatics and computational biology
* medical applications
* transportation systems simulations
* combinatorial and global optimization problems
* structural engineering
* computational electromagnetics
* computer graphics
* semiconductor technology, electronic circuits and system design etc.
Submission Information:
Authors should send one copy of paper with experimental results in
either PS or PDF format at most 20 pages to the workshop organizers
(lyang@stfx.ca or pan@cs.gsu.edu) via electronic mail or three copies via
postal mail. Contributions will be reviewed by at least three reviewers from
both Program Committee and external reviewers for relevance and technical
contents on basis of papers. Accepted papers will be published by IEEE
Computer Society Press as proceedings of the IPDPS workshops. Selected
papers will be appeared on a special issue of the International Journal of
INFORMATION.
Further information about the conference proceedings and registration
fee can be found by web sites:
http://www.ipdps.org/ipdps2001
http://www.stfx.ca/people/lyang/activities/ipdps01-pdseca.html
Important Deadlines:
Paper submission Due November 15, 2000
Notification of Acceptance December 15, 2000
Final camera-ready paper January 15, 2001
Workshop Organizers:
Prof. Laurence T. Yang Prof. Yi Pan
(chair) (Co-Chair)
Department of Computer Science Department of Computer Science
POBox 5000,St.Francis Xavier University Georgia State University
Antigonish, B2G 2W5 Atlanta, GA 30303
Nova Scotia, Canada
Email: lyang@stfx.ca Email: pan@cs.gsu.edu
Technical Committee: (see workshop web site)
Submitted by "Laurence T. Yang" <lyang@stfx.ca>
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KOOL CHIPS WORKSHOP
Abstract submission deadline: November 7th, 2000
Sunday 10th December, 2000 in conjunction with MICRO33, Monterey,
California
PROGRAM
Invited Speakers
Doug Carmean, Intel, Principal Architect Pentium 4
Marc Fleischmann, Director of Low Power Programs, Transmeta Corporation
Jan Rabaey, Professor EECS UC Berkeley, co-director of the Berkeley
Wireless Research Center (BWRC
Theme
The limits imposed by power consumption are becoming an issue in most
areas of computing. The need to limit power consumption is readily
apparent in the case of portable and mobile computer platforms — the
laptop and the cell phone being the most common examples. But the need
to limit power in other computer settings is becoming important too.
This workshop is the third in a series of workshops and tutorials designed
to bring together researchers in the area of architecture-power trade-offs
and provide a forum for them to discuss their preliminary ideas.
The first of these meetings, the Power-Driven Microarchitecture Workshop
was held at ISCA98 in Barcelona, Spain. It helped raise the awareness of
the architecture community to concerns about power issues. This workshop
was followed by a tutorial, the Cool Chips Tutorial at MICRO32 in Haifa,
Israel. It assembled a group of speakers from leading microprocessor
companies to give presentations on what they consider to be their critical
low power issues now and in the future, and some possible solutions to
these problems.
Topics of Interest:
Topics of interest are any subject that addresses power-aware
computing and communications. The focus will be broad and includes on
microarchitecture, architecture, operating systems and compilers.
Paper submission guidelines:
Authors are requested to submit an abstracts of four 8.5 x 11 pages
or less. The abstract should contain a title and a contact address.
All submissions must be by email to tnm@eecs.umich.edu. The preferred
format is pdf, but postscript is also acceptable if it is viewable
by ghostscript.
Important dates:
Paper submission: November 7th, 2000 Notification of
acceptance November 10th, 2000
Camera-ready due November 17th, 2000
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Removing Yourself from SIGARCH Mailing List
If your email address exactly matches the email address recorded
on the SIGARCH list (no forwarding), you can remove yourself with:
mail listserv@acm.org
with message body (not subject):
unsubscribe SIGARCH-MEMBERS
If your email address does *not* match, mail me at infodir_SIGARCH@acm.org,
and I will work to remove you from the list.
--Mark
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