Tomorrow's architecture seminar (1:30 PM in 2310) might be of
interest to the PL seminar audience. It is a practice talk for
the upcoming CGO conference (International Symposium on Code
Generation and Optimization). You are all welcome to attend.
The title and abstract are attached.
-Alaa
Dynamic Binary Translation for Accumulator-Oriented Architectures
By: Ho-Seop Kim, UW-Madison
A dynamic binary translation system for a co-designed virtual machine is
described and evaluated. The underlying hardware directly executes an
accumulator-oriented instruction set that exposes instruction dependence
chains (strands) to a distributed microarchitecture containing a simple
instruction pipeline. To support conventional program binaries, a source
instruction set (Alpha in our study) is dynamically translated to the
target accumulator instruction set. The binary translator identifies
chains of inter-instruction dependences and assigns them to dependence-
carrying accumulators. Because the underlying superscalar
microarchitecture is capable of dynamic instruction scheduling, the
binary translation system does not perform aggressive optimizations or
reschedule code; this significantly reduces binary translation overhead.
Detailed timing simulation of the dynamically translated code running on
an accumulator-based distributed microarchitecture shows the overall
system is capable of achieving similar performance to an ideal out-of-
order superscalar processor, ignoring the significant clock frequency
advantages that the accumulator-based hardware is likely to have. As
part of the study, we evaluate an instruction set modification that
simplifies precise trap implementation. This approach significantly
reduces the number of instructions required for register state copying,
thereby improving performance. We also observe that translation chaining
methods can have substantial impact on the performance, and we evaluate
a number of chaining methods.
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