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Hello,
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Tonia
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From: Architecture [mailto:architecture-bounces@xxxxxxxxxxx] On Behalf Of Tony Nowatzki
Sent: Monday, November 03, 2014 11:53 AM
To: architecture@xxxxxxxxxxx; ecegrad@xxxxxxxxxxxx
Subject: [Architecture] Computer Architecture Seminar: Talk by Professors Mark Hill and David Wood
Professors Mark Hill and David Wood will be giving a talk on Tuesday November 11th titled: "Making Graphics Processing Unit Memory Systems More General Purpose". Details are provided below.
When: Tuesday, November 11th - 4:00pm
Where: 1240 CS
Description:
Graphics Processing Units (GPUs) are being re-purposed to perform general-purpose computations as they offer the potential for better performance and and lower energy than conventional CPUs for some workloads. Effective use of GPGPUs, however often requires the programmer and/or runtime software to explicitly manage the logical name
(address) and/or physical location of data. It is our hypothesis--shared by some--that GPGPUs can be made more generally effective if all CPU-GPU program threads can access data via a uniform virtual address backed by hardware data movement support. To this end, this talk discuss three advances by researchers at Wisconsin and AMD.
LOW-OVERHEAD GPU ADDRESS TRANSLATION. For increased programmability (e.g., pointer-based data structures), memory accessed by CPUs and GPUs should be uniformly virtualized, necessitating compatible address translation support for GPU memory references. However, even a modest GPU might need 100s of translations per cycle with memory access patterns designed for throughput more than locality. We show how a judicious combination of extant CPU MMU ideas satisfies GPU MMU:
per-compute unit TLBs, a shared highly-threaded page table walker, and a shared page walk cache. See Power et al. HPCA 2014.
FAST GPU SYNCHRONIZATION. GPUs have specialized throughput-oriented memory systems optimized for streaming writes but that make expensive currently-rare synchronization (e.g., a flush). A challenge is how to better support irregular applications with finer-grain synchronization without abandoning the throughput-oriented memory systems that differentiate GPUs from CPUs. We offer QuickRelease (QR) that (a) uses a FIFO to enforce the partial order of writes so that synchronization operations can complete without frequent cache flushes and (b) partitions read and write resources to reduce the penalty of writes on read performance. See Hechtman et al. HPCA 2014.
HETEROGENEOUS MEMORY MODELS. Many future heterogeneous systems (e.g., integrated CPUs and GPUs) will (a) support a global memory address space for all components, but (b) have non-global "scoped" synchronization operations since global synchronization is expensive and often unnecessary. We formalize scoped synchronization use by building on conventional data-race-free models (e.g., C++ and Java). Called sequential consistency for heterogeneous-race-free (SC for HRF), the new models guarantee SC for programs with "sufficient" synchronization (no data races) of "sufficient" scope. See Hower et al. ASPLOS 2014.
BIOGRAPHIES. Mark D. Hill (http://www.cs.wisc.edu/~markhill) is Computer Sciences Department Chair and Gene M. Amdahl Professor of Computer Sciences and Electrical & Computer Engineering at the University of Wisconsin--Madison, where he also co-leads the Wisconsin Multifacet project. His research interests include parallel computer system design, memory system design, computer simulation, and transactional memory. He earned a PhD from University of California, Berkeley. He is an ACM Fellow, a Fellow of the IEEE, co-inventor on 30+ patents, and ACM SIGARCH Distinguished Service Award recipient. His accomplishments include teaching more than 1000 students, having 40 Ph.D. progeny so far, developing the 3C cache miss taxonomy (compulsory, capacity, and conflict), and co-developing "sequential consistency for data-race free"
that serves as a foundation of the C++ and Java memory models.
Prof. David A. Wood is a Professor in the Computer Sciences and Electrical and Computer Engineering Departments at the University of Wisconsin, Madison, where he co-leads the Wisconsin Multifacet project.
Dr. Wood was named an ACM Fellow (2005) and IEEE Fellow (2004), received the University of Wisconsin's H.I. Romnes Faculty Fellowship (1999), received the National Science Foundation's Presidential Young Investigator award (1991), and earned his Ph.D. in Computer Sciences from the University of California, Berkeley (1990). Dr. Wood is Chair of ACM Special Interest Group on Computer Architecture (SIGARCH), Area Editor (Computer Systems) of ACM Transactions on Modeling and Computer Simulation, is Associate Editor of ACM Transactions on Architecture and Compiler Optimization, served as Program Committee Chairman of ASPLOS-X (2002), and has served on numerous program committees. Dr. Wood is an ACM Fellow, an IEEE Fellow, and a member of the IEEE Computer Society.
Dr. Wood has published over 70 technical papers and is an inventor on over a dozen U.S. and International patents.
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