Call for Participation in ISCA Tutorial:
gem5: A Multiple-ISA Full System Simulator with Detailed Memory Model
Sunday, June 5, 2011
http://www.gem5.org
The gem5 simulator is a merger of two of the computer architecture
community’s most popular, open source simulators:  M5 and GEMS. The best
 features of each simulator have been combined to provide an 
infrastructure capable of simulating multiple ISAs, CPU models, memory 
system components, cache coherence protocols and interconnection 
networks.  The gem5 simulation team invites users, developers, and all 
other interested parties to participate  in a tutorial that will 
highlight the key aspects of the gem5 simulator .
 The first half of this full-day tutorial will be an organized 
presentation focusing on gem5 usage and capabilities. The second half is 
intended to be more free form where we will answer audience questions on 
specific usage, including modification of the simulator to enable new 
features.
Topics to be discussed include:
- Multiple ISA support (e.g. ARM and x86)
 - Detailed and simple CPU models including “execute-in-execute” 
in-order and out-of-order pipeline models.
- Cache coherence protocols using SLICC
- Interconnection network modeling (Crossbar, Mesh, etc.)
- Checkpointing and fast-forwarding
 We look forward to your participation in the gem5 tutorial and hope that 
by the end of the tutorial you’ll be able to utilize the gem5 
infrastructure in your future research.
Thanks,
The gem5 Simulation Team
 
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