My belief is that your network file just duplicates what ruby would do
internally when you specify CROSSBAR (all-to-all connection through
single-central node).
I personally don't know if you can simulate a bus model.
On Feb 1, 2011, at 4:27 PM, Nilay Vaish wrote:
Joseph, I think both the representations are correct. But whether
your representation will correctly function or not is not known to
me. Another thing to be noticed is that by connecting an L1 cache /
directory to a crossbar switch directly, we might be making some
assumption on what functionality a cache controller provides (over
here I am talking about a real cache controller). By separating the
external nodes and internal nodes, I think we are trying to separate
the routing functionality from the external nodes.
The view I presented above is my personal understanding, so it might
be incorrect.
--
Nilay
On Tue, 1 Feb 2011, Joseph Pusdesris wrote:
Ok, but assuming it was set to FILE_SPECIFIED and I generated the
topology
by another means, which one would be correct? Also, you didn't
mention of a
bus model is feasible.
Thanks!
Joseph
On Mon, Jan 31, 2011 at 3:58 PM, Byn Choi <bynchoi1@xxxxxxxxxxxx>
wrote:
I don't know how M5 handles network topologies, but you'd set
g_NETWORK_TOPOLOGY to CROSSBAR to use crossbar with ruby in GEMS.
The
network configuration file is only relevant when you set that to
FILE_SPECIFIED. By default the scripts generate a 2-D mesh network.
Byn
On Jan 31, 2011, at 2:48 PM, Joseph Pusdesris wrote:
Hello, I am trying to generate several topologies for the M5
simulator
using Ruby's SimpleNetwork and I have a few questions. Am I
correct in
assuming that the SimpleNetwork framework cannot support a bus
model without
modifying the source for PerfectSwitch?
I am also confused about the topologies which are included in the
repository. The default crossbar topology that is included in the
m5
repository generates something along these lines:
ext_node:L1Cache:0 int_node:0 link_latency:1 bw_multiplier:64
ext_node:L1Cache:1 int_node:1 link_latency:1 bw_multiplier:64
ext_node:L1Cache:2 int_node:2 link_latency:1 bw_multiplier:64
ext_node:L1Cache:3 int_node:3 link_latency:1 bw_multiplier:64
ext_node:L2Cache:0 int_node:4 link_latency:1 bw_multiplier:64
ext_node:Directory:0 int_node:5 link_latency:40 bw_multiplier:10
int_node:0 int_node:6 link_latency:40 bw_multiplier:16
int_node:1 int_node:6 link_latency:40 bw_multiplier:16
int_node:2 int_node:6 link_latency:40 bw_multiplier:16
int_node:3 int_node:6 link_latency:40 bw_multiplier:16
int_node:4 int_node:6 link_latency:40 bw_multiplier:16
int_node:5 int_node:6 link_latency:40 bw_multiplier:16
This doesn't make sense to me. Why is there the extra level of
switches
before connecting nodes to the xbar switch? Is it an error in the
repository or am I misunderstanding something? Wouldn't a more
proper
crossbar look like:
ext_node:L1Cache:0 int_node:0 link_latency:1 bw_multiplier:64
ext_node:L1Cache:1 int_node:0 link_latency:1 bw_multiplier:64
ext_node:L1Cache:2 int_node:0 link_latency:1 bw_multiplier:64
ext_node:L1Cache:3 int_node:0 link_latency:1 bw_multiplier:64
ext_node:L2Cache:0 int_node:0 link_latency:1 bw_multiplier:64
ext_node:Directory:0 int_node:0 link_latency:40 bw_multiplier:10
-Joseph
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---
Byn Choi
Ph.D. Candidate in Computer Science
University of Illinois, Urbana-Champaign
_______________________________________________
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---
Byn Choi
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University of Illinois, Urbana-Champaign
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